| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Remove topo sort no-loop assertion, with test | Eddie Hung | 2019-04-24 | 4 | -14/+76 |
| * | Add -nocarry option to synth_xilinx | Eddie Hung | 2019-04-24 | 1 | -5/+14 |
| * | Fix abc9 with (* keep *) wires | Eddie Hung | 2019-04-23 | 2 | -6/+52 |
| * | Refactor into AigerReader::post_process() | Eddie Hung | 2019-04-23 | 2 | -249/+161 |
| * | Tweak | Eddie Hung | 2019-04-22 | 1 | -1/+1 |
| * | Fix for A_WIDTH == 2 but B_WIDTH==3 | Eddie Hung | 2019-04-22 | 1 | -1/+1 |
| * | Trim A_WIDTH by Y_WIDTH-1 | Eddie Hung | 2019-04-22 | 1 | -1/+1 |
| * | Add comment | Eddie Hung | 2019-04-22 | 1 | -0/+3 |
| * | Fix for mux_case_* mappings | Eddie Hung | 2019-04-22 | 1 | -17/+9 |
| * | Fix for non-pow2 width muxes | Eddie Hung | 2019-04-22 | 1 | -9/+18 |
| * | Add synth_xilinx -nomux option | Eddie Hung | 2019-04-22 | 2 | -4/+18 |
| * | Cleanup, call pmux2shiftx even without -nosrl | Eddie Hung | 2019-04-22 | 6 | -45/+30 |
| * | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-22 | 31 | -283/+953 |
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| | * | Temporarily remove 'r' extension | Eddie Hung | 2019-04-22 | 2 | -95/+7 |
| | * | Allow POs to be PIs in XAIG | Eddie Hung | 2019-04-22 | 1 | -7/+4 |
| | * | Remove kernel/cost.cc since master has refactored it | Eddie Hung | 2019-04-22 | 2 | -76/+0 |
| | * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-22 | 46 | -97/+4201 |
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| | | * | Merge pull request #952 from YosysHQ/clifford/fix370 | Clifford Wolf | 2019-04-22 | 1 | -3/+18 |
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| | | | * | Determine correct signedness and expression width in for loop unrolling, fixe... | Clifford Wolf | 2019-04-22 | 1 | -3/+18 |
| | | * | | Merge pull request #951 from YosysHQ/clifford/logdebug | Clifford Wolf | 2019-04-22 | 11 | -53/+183 |
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| | | | * | | Add log_debug() framework | Clifford Wolf | 2019-04-22 | 11 | -53/+183 |
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| | | * | | Merge pull request #949 from YosysHQ/clifford/pmux2shimprove | Clifford Wolf | 2019-04-22 | 2 | -3/+24 |
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| | | | * | | Updaye pmux2shiftx test | Clifford Wolf | 2019-04-22 | 1 | -2/+2 |
| | | | * | | Add full_pmux feature to pmux2shiftx | Clifford Wolf | 2019-04-22 | 1 | -1/+22 |
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| | | * | | Merge pull request #953 from YosysHQ/clifford/fix948 | Clifford Wolf | 2019-04-22 | 1 | -0/+8 |
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| | | | * | | Add support for zero-width signals to Verilog back-end, fixes #948 | Clifford Wolf | 2019-04-22 | 1 | -0/+8 |
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| | * | | | Merge remote-tracking branch 'origin/clifford/libwb' into xaig | Eddie Hung | 2019-04-21 | 1 | -1/+1 |
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| | * | | | | Convert to use #945 | Eddie Hung | 2019-04-21 | 2 | -9/+3 |
| | * | | | | Merge remote-tracking branch 'origin/clifford/libwb' into xaig | Eddie Hung | 2019-04-21 | 8 | -38/+123 |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-20 | 18 | -59/+195 |
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| | * | | | | | | ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set | Eddie Hung | 2019-04-19 | 2 | -4/+7 |
| | * | | | | | | Select to find union of both sets on stack | Eddie Hung | 2019-04-19 | 1 | -1/+1 |
| | * | | | | | | Fixes for simple_abc9 tests | Eddie Hung | 2019-04-19 | 1 | -4/+8 |
| | * | | | | | | Do not assume inst_module is always present | Eddie Hung | 2019-04-19 | 1 | -12/+9 |
| | * | | | | | | ignore_boxes -> holes_mode | Eddie Hung | 2019-04-19 | 1 | -6/+5 |
| | * | | | | | | Make SB_DFF whitebox | Eddie Hung | 2019-04-19 | 3 | -3/+3 |
| | * | | | | | | Fix SB_DFF comb model | Eddie Hung | 2019-04-18 | 2 | -3/+3 |
| | * | | | | | | Missing close bracket | Eddie Hung | 2019-04-18 | 1 | -1/+1 |
| | * | | | | | | Annotate SB_DFF* with abc_flop and abc_box_id | Eddie Hung | 2019-04-18 | 1 | -22/+49 |
| | * | | | | | | Add SB_DFF* to boxes | Eddie Hung | 2019-04-18 | 3 | -6/+306 |
| | * | | | | | | Add flop support for write_xaiger | Eddie Hung | 2019-04-18 | 1 | -11/+83 |
| | * | | | | | | read_aiger to parse 'r' extension | Eddie Hung | 2019-04-18 | 1 | -0/+18 |
| | * | | | | | | Spelling | Eddie Hung | 2019-04-18 | 1 | -1/+1 |
| | * | | | | | | Use new -wb flag for ABC flow | Eddie Hung | 2019-04-18 | 4 | -48/+36 |
| | * | | | | | | write_json to not write contents (cells/wires) of whiteboxes | Eddie Hung | 2019-04-18 | 1 | -56/+59 |
| | * | | | | | | Ignore 'whitebox' attr in flatten with "-wb" option | Eddie Hung | 2019-04-18 | 2 | -7/+21 |
| | * | | | | | | Also update Makefile.inc | Eddie Hung | 2019-04-18 | 1 | -7/+6 |
| | * | | | | | | Make SB_LUT4 a blackbox | Eddie Hung | 2019-04-18 | 3 | -3/+3 |
| | * | | | | | | Fix rename | Eddie Hung | 2019-04-18 | 1 | -0/+0 |
| | * | | | | | | Rename to abc_*.{box,lut} | Eddie Hung | 2019-04-18 | 6 | -0/+0 |
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index : iCE40/yosys | |
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