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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 17:59:56 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 17:59:56 -0700 |
| commit | 60026842b20e04affe60a7871fd14bb544add37b (patch) | |
| tree | be50d4f7dc8c11a91f9901691352edeb8e741f09 /techlibs | |
| parent | 26e461f47da12b79e5b6682f692d81e2721ca0c0 (diff) | |
| download | yosys-60026842b20e04affe60a7871fd14bb544add37b.tar.gz yosys-60026842b20e04affe60a7871fd14bb544add37b.tar.bz2 yosys-60026842b20e04affe60a7871fd14bb544add37b.zip | |
Tweak
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 10dbb8b9a..4275c03e6 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -179,7 +179,7 @@ module \$shiftx (A, B, Y); assign A_i[i] = A[i*2]; \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y)); end - else if (B_WIDTH < 3 || A_WIDTH == 2**2) begin + else if (B_WIDTH < 3 || A_WIDTH <= 4) begin wire _TECHMAP_FAIL_ = 1; end else if (B_WIDTH == 3) begin |