| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 16 | -54/+54 |
| * | ecp5: Fixing miscellaneous sim model issues | David Shah | 2018-07-16 | 1 | -2/+2 |
| * | ecp5: Fixing 'X' issues with LUT simulation models | David Shah | 2018-07-16 | 1 | -6/+19 |
| * | ecp5: ECP5 synthesis fixes | David Shah | 2018-07-16 | 3 | -15/+32 |
| * | ecp5: Adding synchronous set/reset support | David Shah | 2018-07-14 | 2 | -21/+42 |
| * | ecp5: Add DRAM match rule | David Shah | 2018-07-13 | 1 | -0/+4 |
| * | ecp5: Cells and mappings fixes | David Shah | 2018-07-13 | 2 | -5/+5 |
| * | ecp5: Fixing arith_map | David Shah | 2018-07-13 | 1 | -4/+5 |
| * | ecp5: Initial arith_map implementation | David Shah | 2018-07-13 | 3 | -6/+80 |
| * | ecp5: Adding basic synth_ecp5 based on synth_ice40 | David Shah | 2018-07-13 | 3 | -7/+345 |
| * | ecp5: Adding DFF maps | David Shah | 2018-07-13 | 2 | -1/+30 |
| * | ecp5: Adding DRAM map | David Shah | 2018-07-13 | 3 | -1/+76 |
| * | ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7 | David Shah | 2018-07-13 | 2 | -0/+473 |
| * | ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC | David Shah | 2018-07-13 | 1 | -2/+6 |
| * | Add "synth_ice40 -json" | Clifford Wolf | 2018-06-13 | 1 | -9/+22 |
| * | Fix ice40_opt for cases where a port is connected to a signal with width != 1 | Clifford Wolf | 2018-06-11 | 1 | -9/+25 |
| * | Make -nordff the default in "prep" | Clifford Wolf | 2018-05-30 | 1 | -9/+13 |
| * | Avoid mixing module port declaration styles in ice40 cells_sim.v | Olof Kindgren | 2018-05-17 | 1 | -43/+23 |
| * | Merge pull request #537 from mithro/yosys-vpr | Clifford Wolf | 2018-05-04 | 4 | -11/+48 |
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| | * | Improving vpr output support. | Tim 'mithro' Ansell | 2018-04-18 | 4 | -7/+40 |
| | * | synth_ice40: Rework the vpr blif output slightly. | Tim 'mithro' Ansell | 2018-04-18 | 1 | -4/+8 |
| * | | Add "synth_intel --noiopads" | Clifford Wolf | 2018-04-30 | 1 | -2/+11 |
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| * | Add "synth_ice40 -nodffe" | Clifford Wolf | 2018-04-16 | 1 | -2/+11 |
| * | Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal val... | c60k28 | 2018-03-31 | 11 | -178/+233 |
| * | coolrunner2: Add an ANDTERM/XOR between chained FFs | Robert Ou | 2018-03-31 | 1 | -0/+58 |
| * | coolrunner2: Split multi-bit nets | Robert Ou | 2018-03-31 | 1 | -0/+1 |
| * | coolrunner2: Add extraction for TFFs | Robert Ou | 2018-03-31 | 3 | -0/+54 |
| * | Squelch trailing whitespace, including meta-whitespace | Larry Doolittle | 2018-03-11 | 4 | -16/+16 |
| * | Add Xilinx RAM64X1D and RAM128X1D simulation models | Clifford Wolf | 2018-03-07 | 4 | -23/+30 |
| * | Add "synth -noshare" | Clifford Wolf | 2018-03-04 | 1 | -2/+11 |
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -0/+24 |
| * | coolrunner2: Move LOC attributes onto the IO cells | Robert Ou | 2018-01-17 | 1 | -0/+2 |
| * | Add "dffinit -highlow" and fix synth_intel | Clifford Wolf | 2018-01-09 | 1 | -1/+1 |
| * | Fix minor typo in "prep" help message | Clifford Wolf | 2017-12-19 | 1 | -1/+1 |
| * | Fix port names in SB_IO_OD | Graham Edgecombe | 2017-12-10 | 1 | -18/+18 |
| * | Remove trailing comma from SB_IO_OD port list | Graham Edgecombe | 2017-12-10 | 1 | -1/+1 |
| * | Fix spelling in -vpr help for synth_ice40 | Tim Ansell | 2017-12-08 | 1 | -1/+1 |
| * | Merge pull request #462 from daveshah1/up5k | Clifford Wolf | 2017-11-28 | 1 | -0/+263 |
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| | * | Add remaining UltraPlus cells to ice40 techlib | David Shah | 2017-11-28 | 1 | -0/+263 |
| * | | Merge pull request #455 from daveshah1/up5k | Clifford Wolf | 2017-11-18 | 1 | -0/+103 |
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| | * | Remove unnecessary keep attributes | David Shah | 2017-11-18 | 1 | -5/+5 |
| | * | Merge branch 'master' into up5k | David Shah | 2017-11-17 | 2 | -5/+29 |
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| | * | | Add some UltraPlus cells to ice40 techlib | David Shah | 2017-11-16 | 1 | -0/+103 |
| * | | | Merge pull request #453 from dh73/master | Clifford Wolf | 2017-11-18 | 10 | -5/+312 |
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| | * | | Initial Cyclone 10 support | dh73 | 2017-11-08 | 5 | -1/+308 |
| | * | | Organizing Speedster file names | dh73 | 2017-11-08 | 5 | -4/+4 |
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| * / | Add "synth_ice40 -vpr" | Clifford Wolf | 2017-11-16 | 2 | -5/+29 |
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| * | Clean whitespace and permissions in techlibs/intel | Larry Doolittle | 2017-10-05 | 21 | -190/+190 |
| * | Rename "write_verilog -nobasenradix" to "write_verilog -decimal" | Clifford Wolf | 2017-10-03 | 1 | -4/+1 |
| * | Tested and working altsyncarm without init files | dh73 | 2017-10-01 | 2 | -57/+59 |
