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| author | David Shah <davey1576@gmail.com> | 2018-07-13 15:49:59 +0200 |
|---|---|---|
| committer | David Shah <davey1576@gmail.com> | 2018-07-13 15:49:59 +0200 |
| commit | b0fea67cc66ceac64e2cb71874c36cde21aa34df (patch) | |
| tree | db64131445c2bec3feee7adee9d266d92438cd4b /techlibs | |
| parent | 11c916840d127d7e32fd9689f1c86cdc847352e0 (diff) | |
| download | yosys-b0fea67cc66ceac64e2cb71874c36cde21aa34df.tar.gz yosys-b0fea67cc66ceac64e2cb71874c36cde21aa34df.tar.bz2 yosys-b0fea67cc66ceac64e2cb71874c36cde21aa34df.zip | |
ecp5: Fixing arith_map
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ecp5/arith_map.v | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v index 3c2b86deb..cf21ee80e 100644 --- a/techlibs/ecp5/arith_map.v +++ b/techlibs/ecp5/arith_map.v @@ -51,7 +51,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); wire [Y_WIDTH2-1:0] AA = A_buf; wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf; wire [Y_WIDTH2-1:0] C = {CO, CI}; - wire [Y_WIDTH2-1:0] FCO; + wire [Y_WIDTH2-1:0] FCO, Y1; genvar i; generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice @@ -64,14 +64,15 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); .CIN(C[i]), .A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1), .A1(AA[i+1]), .B1(BB[i]), .C1(1'b0), .D1(1'b1), - .S0(F0), .S1(F1), + .S0(Y[i]), .S1(Y1[i]), .COUT(FCO[i]) ); assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i])); - if (i < Y_WIDTH) + if (i < Y_WIDTH) begin assign CO[i+1] = FCO[i]; - + assign Y[i+1] = Y1[i]; + end end endgenerate assign X = AA ^ BB; |