| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor | Eddie Hung | 2019-12-30 | 6 | -121/+673 |
| |\ | |||||
| | * | Do not offset FD* box timings due to -46ps Tsu | Eddie Hung | 2019-12-30 | 1 | -12/+21 |
| | * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-30 | 10 | -32/+377 |
| | |\ | |||||
| | * | | Tidy up abc9_map.v | Eddie Hung | 2019-12-30 | 1 | -103/+103 |
| | * | | Add "synth_xilinx -dff" option, cleanup abc9 | Eddie Hung | 2019-12-30 | 2 | -2/+98 |
| | * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-20 | 1 | -24/+10 |
| | |\ \ | |||||
| | * \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-20 | 4 | -172/+240 |
| | |\ \ \ | |||||
| | * | | | | Add RAM{32,64}M to abc9_map.v | Eddie Hung | 2019-12-19 | 1 | -0/+78 |
| | * | | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t | Eddie Hung | 2019-12-19 | 5 | -36/+55 |
| | * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-19 | 14 | -81/+995 |
| | |\ \ \ \ | |||||
| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-12 | 13 | -30/+32 |
| | |\ \ \ \ \ | |||||
| | * | | | | | | abc9_map.v: fix Xilinx LUTRAM | Eddie Hung | 2019-12-12 | 1 | -6/+6 |
| | * | | | | | | Fix comment | Eddie Hung | 2019-12-09 | 1 | -1/+1 |
| | * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 7 | -745/+1138 |
| | |\ \ \ \ \ \ | |||||
| | * | | | | | | | Remove creation of $abc9_control_wire | Eddie Hung | 2019-12-06 | 1 | -16/+6 |
| | * | | | | | | | abc9 to use mergeability class to differentiate sync/async | Eddie Hung | 2019-12-06 | 1 | -12/+15 |
| | * | | | | | | | Remove clkpart | Eddie Hung | 2019-12-05 | 1 | -4/+0 |
| | * | | | | | | | Revert "Special abc9_clock wire to contain only clock signal" | Eddie Hung | 2019-12-05 | 1 | -10/+12 |
| | * | | | | | | | Missing wire declaration | Eddie Hung | 2019-12-04 | 1 | -0/+1 |
| | * | | | | | | | abc9_map.v to transform INIT=1 to INIT=0 | Eddie Hung | 2019-12-04 | 1 | -118/+201 |
| | * | | | | | | | Oh deary me | Eddie Hung | 2019-12-04 | 1 | -4/+4 |
| | * | | | | | | | output reg Q -> output Q to suppress warning | Eddie Hung | 2019-12-04 | 1 | -8/+8 |
| | * | | | | | | | abc9_map.v to do `zinit' and make INIT = 1'b0 | Eddie Hung | 2019-12-04 | 1 | -70/+112 |
| | * | | | | | | | Add abc9_init wire, attach to abc9_flop cell | Eddie Hung | 2019-12-03 | 1 | -2/+12 |
| | * | | | | | | | Revert "Add INIT value to abc9_control" | Eddie Hung | 2019-12-03 | 1 | -8/+8 |
| | * | | | | | | | techmap abc_unmap.v before xilinx_srl -fixed | Eddie Hung | 2019-12-03 | 1 | -6/+5 |
| | * | | | | | | | Add INIT value to abc9_control | Eddie Hung | 2019-12-02 | 1 | -8/+8 |
| | * | | | | | | | clkpart -unpart into 'finalize' | Eddie Hung | 2019-11-28 | 1 | -3/+4 |
| | * | | | | | | | ean call after abc{,9} | Eddie Hung | 2019-11-27 | 1 | -1/+2 |
| | * | | | | | | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff | Eddie Hung | 2019-11-27 | 3 | -25/+30 |
| | |\ \ \ \ \ \ \ | |||||
| | * | | | | | | | | Move 'clean' from map_luts to finalize | Eddie Hung | 2019-11-26 | 1 | -1/+1 |
| | * | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-25 | 3 | -5/+11 |
| | |\ \ \ \ \ \ \ \ | |||||
| | * | | | | | | | | | Special abc9_clock wire to contain only clock signal | Eddie Hung | 2019-11-25 | 1 | -12/+10 |
| | * | | | | | | | | | For abc9, run clkpart before ff_map and after abc9 | Eddie Hung | 2019-11-23 | 1 | -0/+2 |
| | * | | | | | | | | | Merge branch 'eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -0/+2 |
| | |\ \ \ \ \ \ \ \ \ | |||||
| | * \ \ \ \ \ \ \ \ \ | Merge branch 'eddie/xaig_dff_adff' into xaig_dff | Eddie Hung | 2019-11-21 | 1 | -12/+16 |
| | |\ \ \ \ \ \ \ \ \ \ | |||||
| | | * | | | | | | | | | | Do not drop async control signals in abc_map.v | Eddie Hung | 2019-11-19 | 1 | -12/+16 |
| | * | | | | | | | | | | | Add blackbox model for $__ABC9_FF_ so that clock partitioning works | Eddie Hung | 2019-11-20 | 1 | -0/+3 |
| | * | | | | | | | | | | | Fix INIT values | Eddie Hung | 2019-11-20 | 1 | -4/+4 |
| | |/ / / / / / / / / / | |||||
| | * | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-19 | 41 | -23094/+31993 |
| | |\ \ \ \ \ \ \ \ \ \ | |||||
| | * \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-08 | 1 | -5/+9 |
| | |\ \ \ \ \ \ \ \ \ \ \ | |||||
| | * | | | | | | | | | | | | Cleanup | Eddie Hung | 2019-10-07 | 1 | -7/+2 |
| | * | | | | | | | | | | | | Rename $currQ to $abc9_currQ | Eddie Hung | 2019-10-07 | 1 | -46/+46 |
| | * | | | | | | | | | | | | Update comments in abc9_map.v | Eddie Hung | 2019-10-07 | 1 | -131/+57 |
| | * | | | | | | | | | | | | Remove -D_ABC9 | Eddie Hung | 2019-10-07 | 1 | -2/+0 |
| | * | | | | | | | | | | | | Do not require changes to cells_sim.v; try and work out comb model | Eddie Hung | 2019-10-05 | 4 | -230/+200 |
| | * | | | | | | | | | | | | abc -> abc9 | Eddie Hung | 2019-10-04 | 1 | -3/+3 |
| | * | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-04 | 4 | -181/+9 |
| | |\ \ \ \ \ \ \ \ \ \ \ \ | |||||
| | * | | | | | | | | | | | | | Use read_args for read_verilog | Eddie Hung | 2019-10-04 | 1 | -3/+6 |
| | * | | | | | | | | | | | | | Fix merge issues | Eddie Hung | 2019-10-04 | 2 | -9/+10 |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |