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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-04 23:04:40 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-04 23:04:40 -0800 |
| commit | 0d248dd7bae707505071b309b55bac75facccab8 (patch) | |
| tree | 50db75ab28e5c0565e5e24bbbb6c7f26abcf6058 /techlibs | |
| parent | 19bc429482418aa42861ca0f195d86bc9577e320 (diff) | |
| download | yosys-0d248dd7bae707505071b309b55bac75facccab8.tar.gz yosys-0d248dd7bae707505071b309b55bac75facccab8.tar.bz2 yosys-0d248dd7bae707505071b309b55bac75facccab8.zip | |
Missing wire declaration
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/abc9_map.v | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 3fa5f5a1c..d2159f82d 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -192,6 +192,7 @@ module FDCE (output Q, input C, CE, D, CLR); endmodule module FDCE_1 (output Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; + wire QQ, $nextQ, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; FDPE_1 #( |