Do not require changes to cells_sim.v; try and work out comb model

4 files changed, 200 insertions, 230 deletions

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 05063f86d..ef7a1a09f 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -49,8 +49,57 @@ module FDRE (output reg Q, input C, CE, D, R);
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
   );
-  wire _TECHMAP_REPLACE_.$currQ = Q;
+  // `abc9' requires that complex flops be split into a combinatorial box
+  //   feeding a simple flop ($_ABC9_FF_).
+  // Yosys will automatically analyse the simulation model (described in
+  //   cells_sim.v) and detach any $_DFF_P_ or $_DFF_N_ cells present in
+  //   order to extract the combinatorial control logic left behind.
+  //   Specifically, a simulation model similar to the one below:
+  //
+  //           ++===================================++
+  //           ||                        Sim model  ||
+  //           ||      /\/\/\/\                     ||
+  //       D -->>-----<        >     +------+       ||
+  //       R -->>-----<  Comb. >     |$_DFF_|       ||
+  //      CE -->>-----<  logic >-----| [NP]_|---+---->>-- Q
+  //           ||  +--<        >     +------+   |   ||
+  //           ||  |   \/\/\/\/                 |   ||
+  //           ||  |                            |   ||
+  //           ||  +----------------------------+   ||
+  //           ||                                   ||
+  //           ++===================================++
+  //
+  //   is transformed into:
+  //
+  //           ++==================++
+  //           ||         Comb box ||
+  //           ||                  ||
+  //           ||      /\/\/\/\    ||
+  //      D  -->>-----<        >   ||            +------+
+  //      R  -->>-----<  Comb. >   ||            |$_ABC_|
+  //     CE  -->>-----<  logic >--->>-- $nextQ --|  FF_ |--+-->> Q
+  // $currQ +-->>-----<        >   ||            +------+  |
+  //        |  ||      \/\/\/\/    ||                      |
+  //        |  ||                  ||                      |
+  //        |  ++==================++                      |
+  //        |                                              |
+  //        +----------------------------------------------+
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  // Special signal indicating control domain
+  //   (which, combined with this cell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
+  // Special signal indicating the current value of the flip-flop
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `$currQ' wire.
+  wire _TECHMAP_REPLACE_.$currQ = Q;
 endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
@@ -60,8 +109,22 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
   );
-  wire _TECHMAP_REPLACE_.$currQ = Q;
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
+  // Special signal indicating the current value of the flip-flop
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `$currQ' wire.
+  wire _TECHMAP_REPLACE_.$currQ = Q;
 endmodule
 
 module FDCE (output reg Q, input C, CE, D, CLR);
@@ -69,18 +132,38 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  wire $currQ, $nextQ;
+  wire $nextQ, $currQ;
   FDCE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_CLR_INVERTED(IS_CLR_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ),  .C(C), .CE(CE), .CLR(CLR)
+    .D(D), .Q($nextQ),  .C(C), .CE(CE), .CLR(IS_CLR_INVERTED)
+                                         // ^^^ Note that async
+                                         //     control is disabled
+                                         //     and captured by
+                                         //     $__ABC9_ASYNC below
   );
-  wire _TECHMAP_REPLACE_.$currQ = Q;
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
-  \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
+  // Since this is an async flop, async behaviour is also dealt with
+  //   using the $_ABC9_ASYNC box by abc9_map.v
+  \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
+  // Special signal indicating the current value of the flip-flop
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `$currQ' wire.
+  wire _TECHMAP_REPLACE_.$currQ = $currQ;
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
@@ -88,11 +171,29 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
   FDCE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(1'b0)
+                                         // ^^^ Note that async
+                                         //     control is disabled
+                                         //     and captured by
+                                         //     $__ABC9_ASYNC below
   );
-  wire _TECHMAP_REPLACE_.$currQ = Q;
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
-  \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q));
+  \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q));
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
+  // Special signal indicating the current value of the flip-flop
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `$currQ' wire.
+  wire _TECHMAP_REPLACE_.$currQ = $currQ;
 endmodule
 
 module FDPE (output reg Q, input C, CE, D, PRE);
@@ -107,11 +208,29 @@ module FDPE (output reg Q, input C, CE, D, PRE);
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_PRE_INVERTED(IS_PRE_INVERTED),
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(IS_PRE_INVERTED)
+                                         // ^^^ Note that async
+                                         //     control is disabled
+                                         //     and captured by
+                                         //     $__ABC9_ASYNC below
   );
-  wire _TECHMAP_REPLACE_.$currQ = Q;
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
-  \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
+  \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
+  // Special signal indicating the current value of the flip-flop
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `$currQ' wire.
+  wire _TECHMAP_REPLACE_.$currQ = $currQ;
 endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
@@ -119,11 +238,29 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   FDPE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(1'b0)
+                                         // ^^^ Note that async
+                                         //     control is disabled
+                                         //     and captured by
+                                         //     $__ABC9_ASYNC below
   );
-  wire _TECHMAP_REPLACE_.$currQ = Q;
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
-  \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q));
+  \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q));
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
+  // Special signal indicating the current value of the flip-flop
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `$currQ' wire.
+  wire _TECHMAP_REPLACE_.$currQ = $currQ;
 endmodule
 
 module FDSE (output reg Q, input C, CE, D, S);
@@ -140,8 +277,22 @@ module FDSE (output reg Q, input C, CE, D, S);
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
   );
-  wire _TECHMAP_REPLACE_.$currQ = Q;
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
+  // Special signal indicating the current value of the flip-flop
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `$currQ' wire.
+  wire _TECHMAP_REPLACE_.$currQ = Q;
 endmodule
 module FDSE_1 (output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b0;
@@ -151,8 +302,22 @@ module FDSE_1 (output reg Q, input C, CE, D, S);
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
   );
-  wire _TECHMAP_REPLACE_.$currQ = Q;
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
+  // Special signal indicating the current value of the flip-flop
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `$currQ' wire.
+  wire _TECHMAP_REPLACE_.$currQ = Q;
 endmodule
 
 module RAM32X1D (
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index 74b5cf66a..c17d6744a 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -30,11 +30,8 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
                 : (S0 ? I1 : I0);
 endmodule
 
-module \$__ABC_FF_ (input D, output Q);
-endmodule
-
 (* abc_box_id = 1000 *)
-module \$__ABC_ASYNC (input A, S, output Y);
+module \$__ABC9_ASYNC (input A, S, output Y);
 endmodule
 
 // Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box
index 6814b101f..24b1898a4 100644
--- a/techlibs/xilinx/abc9_xc7.box
+++ b/techlibs/xilinx/abc9_xc7.box
@@ -44,7 +44,7 @@ CARRY4 4 1 10 8
 # Box to emulate async behaviour of FD[CP]*
 # Inputs: A S
 # Outputs: Y
-$__ABC_ASYNC 1000 0 2 1
+$__ABC9_ASYNC 1000 0 2 1
 0 764
 
 # The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 309ee500a..35d9aac96 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -258,33 +258,10 @@ module FDRE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
-`ifdef _ABC9
-  // `abc9' requires that complex flops be split into a combinatorial
-  //   box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
-
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
-  wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
-  wire [3:0] $abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
-  always @* Q = \$nextQ ;
-`else
-  assign \$currQ = Q;
   generate case (|IS_C_INVERTED)
-    1'b0: always @(posedge C) Q <= \$nextQ ;
-    1'b1: always @(negedge C) Q <= \$nextQ ;
+    1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+    1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase endgenerate
-`endif
 endmodule
 
 (* abc9_box_id=1002, lib_whitebox, abc9_flop *)
@@ -297,30 +274,7 @@ module FDRE_1 (
 );
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ;
-`ifdef _ABC9
-  // `abc9' requires that complex flops be split into a combinatorial
-  //   box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
-
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
-  wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
-  wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
-  always @* Q = \$nextQ ;
-`else
-  assign \$currQ = Q;
-  always @(negedge C) Q <= \$nextQ ;
-`endif
+  always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
 (* abc9_box_id=1003, lib_whitebox, abc9_flop *)
@@ -341,37 +295,12 @@ module FDCE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
-`ifdef _ABC9
-  // `abc9' requires that complex flops be split into a combinatorial
-  //   box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
-  // Since this is an async flop, async behaviour is also dealt with
-  //   using the $_ABC9_ASYNC box by abc9_map.v
-
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
-  wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
-  wire [3:0] $abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
-  always @* Q = \$nextQ ;
-`else
-  assign \$currQ = Q;
   generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
-    2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
-    2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
-    2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
-    2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
+    2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+    2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+    2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+    2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase endgenerate
-`endif
 endmodule
 
 (* abc9_box_id=1004, lib_whitebox, abc9_flop *)
@@ -384,32 +313,7 @@ module FDCE_1 (
 );
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
-`ifdef _ABC9
-  // `abc9' requires that complex flops be split into a combinatorial
-  //   box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
-  // Since this is an async flop, async behaviour is also dealt with
-  //   using the $_ABC9_ASYNC box by abc9_map.v
-
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
-  wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
-  wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
-  always @* Q = \$nextQ ;
-`else
-  assign \$currQ = Q;
-  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ;
-`endif
+  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
 (* abc9_box_id=1005, lib_whitebox, abc9_flop *)
@@ -430,37 +334,12 @@ module FDPE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
-`ifdef _ABC9
-  // `abc9' requires that complex flops be split into a combinatorial
-  //   box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
-  // Since this is an async flop, async behaviour is also dealt with
-  //   using the $_ABC9_ASYNC box by abc9_map.v
-
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
-  wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
-  wire [3:0] $abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
-  always @* Q = \$nextQ ;
-`else
-  assign \$currQ = Q;
   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
-    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
-    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
-    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
-    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
+    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ;
+    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ;
+    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ;
+    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ;
   endcase endgenerate
-`endif
 endmodule
 
 (* abc9_box_id=1006, lib_whitebox, abc9_flop *)
@@ -473,32 +352,7 @@ module FDPE_1 (
 );
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
-`ifdef _ABC9
-  // `abc9' requires that complex flops be split into a combinatorial
-  //   box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
-  // Since this is an async flop, async behaviour is also dealt with
-  //   using the $_ABC9_ASYNC box by abc9_map.v
-
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
-  wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
-  wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
-  always @* Q = \$nextQ ;
-`else
-  assign \$currQ = Q;
-  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ;
-`endif
+  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
 (* abc9_box_id=1007, lib_whitebox, abc9_flop *)
@@ -519,33 +373,10 @@ module FDSE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
-`ifdef _ABC9
-  // `abc9' requires that complex flops be split into a combinatorial
-  //   box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
-
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
-  wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
-  wire [3:0] $abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
-  always @* Q = \$nextQ ;
-`else
-  assign \$currQ = Q;
   generate case (|IS_C_INVERTED)
-    1'b0: always @(posedge C) Q <= \$nextQ ;
-    1'b1: always @(negedge C) Q <= \$nextQ ;
+    1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+    1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase endgenerate
-`endif
 endmodule
 
 (* abc9_box_id=1008, lib_whitebox, abc9_flop *)
@@ -558,30 +389,7 @@ module FDSE_1 (
 );
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ;
-`ifdef _ABC9
-  // `abc9' requires that complex flops be split into a combinatorial
-  //   box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
-
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
-  wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
-  wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
-  always @* Q = \$nextQ ;
-`else
-  assign \$currQ = Q;
-  always @(negedge C) Q <= \$nextQ ;
-`endif
+  always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
 module LDCE (