iCE40/yosys - clone of https://github.com/YosysHQ/yosys

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From 679f68410271a32f200e48b501027f68bd114d5c Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Wed, 21 Aug 2019 14:55:56 +0100
Subject: [PATCH] clk-raspberrypi: Also support v3d clock

Signed-off-by: popcornmix <popcornmix@gmail.com>
---
 drivers/clk/bcm/clk-raspberrypi.c | 497 ++++++++++++++++++++++++------
 1 file changed, 408 insertions(+), 89 deletions(-)

--- a/drivers/clk/bcm/clk-raspberrypi.c
+++ b/drivers/clk/bcm/clk-raspberrypi.c
@@ -15,33 +15,103 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
-
+#include <dt-bindings/clock/bcm2835.h>
 #include <soc/bcm2835/raspberrypi-firmware.h>
 
 #define RPI_FIRMWARE_ARM_CLK_ID		0x00000003
+#define RPI_FIRMWARE_V3D_CLK_ID		0x00000005
 
 #define RPI_FIRMWARE_STATE_ENABLE_BIT	BIT(0)
 #define RPI_FIRMWARE_STATE_WAIT_BIT	BIT(1)
 
-/*
- * Even though the firmware interface alters 'pllb' the frequencies are
- * provided as per 'pllb_arm'. We need to scale before passing them trough.
- */
-#define RPI_FIRMWARE_PLLB_ARM_DIV_RATE	2
-
 #define A2W_PLL_FRAC_BITS		20
 
+#define SOC_BCM2835		BIT(0)
+#define SOC_BCM2711		BIT(1)
+#define SOC_ALL			(SOC_BCM2835 | SOC_BCM2711)
+
 struct raspberrypi_clk {
 	struct device *dev;
 	struct rpi_firmware *firmware;
 	struct platform_device *cpufreq;
+};
+
+typedef int (*raspberrypi_clk_register)(struct raspberrypi_clk *rpi,
+					      const void *data);
+
+
+/* assignment helper macros for different clock types */
+#define _REGISTER(f, s, ...) { .clk_register = (raspberrypi_clk_register)f, \
+			       .supported = s,				\
+			       .data = __VA_ARGS__ }
+#define REGISTER_PLL(s, ...)	_REGISTER(&raspberrypi_register_pll,	\
+					  s,				\
+					  &(struct raspberrypi_pll_data)	\
+					  {__VA_ARGS__})
+#define REGISTER_PLL_DIV(s, ...) _REGISTER(&raspberrypi_register_pll_divider, \
+					   s,				  \
+					   &(struct raspberrypi_pll_divider_data) \
+					   {__VA_ARGS__})
+#define REGISTER_CLK(s, ...)	_REGISTER(&raspberrypi_register_clock,	\
/tr>

	Commit message (Collapse)	Author	Age	Files	Lines
...
*	machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE.	William D. Jones	2021-02-23	1	-1/+1
\|
*	machxo2: Fix cells_sim typo where OFX1 was multiply-driven.	William D. Jones	2021-02-23	1	-1/+1
\|
*	machxo2: synth_machxo2 now maps ports to FACADE_IO.	William D. Jones	2021-02-23	2	-0/+12
\|
*	machxo2: Add initial value for Q in FACADE_FF.	William D. Jones	2021-02-23	1	-0/+2
\|
*	machxo2: Add FACADE_IO simulation model. More comments on models.	William D. Jones	2021-02-23	1	-0/+25
\|
*	machxo2: Add FACADE_SLICE simulation model.	William D. Jones	2021-02-23	1	-0/+83
\|
*	machxo2: Improve FACADE_FF simulation model.	William D. Jones	2021-02-23	1	-12/+20
\|
*	machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice.	William D. Jones	2021-02-23	2	-4/+4
\|
*	machxo2: Add dff.ys test, fix another cells_map.v typo.	William D. Jones	2021-02-23	1	-1/+1
\|
*	machxo2: Fix more oversights in machxo2 models. logic.ys test passes.	William D. Jones	2021-02-23	2	-2/+6
\|
*	machxo2: Fix typos. test/arch/run-test.sh passes.	William D. Jones	2021-02-23	2	-2/+2
\|
*	machxo2: Create basic techlibs and synth_machxo2 pass.	William D. Jones	2021-02-23	4	-0/+320
\|
*	Merge pull request #2585 from YosysHQ/dave/nexus-dotproduct	gatecat	2021-02-12	1	-0/+115
\|\ \| \| \| \|	nexus: Add MULTADDSUB9X9WIDE sim model
\| *	nexus: Add MULTADDSUB9X9WIDE sim model	David Shah	2020-12-08	1	-0/+115
\| \| \| \| \| \| \| \|	Signed-off-by: David Shah <dave@ds0.me>
* \|	verilog: significant block scoping improvements	Zachary Snow	2021-01-31	5	-81/+89
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* \|	xilinx_dffopt: Don't crash on missing IS_*_INVERTED.	Marcelina Kościelnicka	2021-01-27	1	-3/+3
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	The presence of IS__INVERTED on FD cells follows Vivado, which apparently has been decided by a dice roll. Just assume false if the parameter doesn't exist. Fixes #2559.
* \|	xilinx: Add FDRSE_1, FDCPE_1.	Marcelina Kościelnicka	2021-01-27	1	-0/+80
\| \|
* \|	Fix some trivial typos.	Tom Verbeure	2021-01-03	1	-5/+5
\| \|
* \|	Merge pull request #2480 from YosysHQ/dave/nexus-lram	whitequark	2021-01-01	5	-1/+227
\|\\| \| \| \| \|	nexus: Add LRAM inference
\| *	nexus: Add LRAM inference	David Shah	2020-12-07	5	-1/+227
\| \| \| \| \| \| \| \|	Signed-off-by: David Shah <dave@ds0.me>
* \|	xilinx: Add some missing blackbox cells.	Marcelina Kościelnicka	2020-12-21	3	-798/+6276
\| \|
* \|	xilinx: Regenerate cells_xtra.v using Vivado 2020.2	Marcelina Kościelnicka	2020-12-21	2	-42/+49
\| \|
* \|	xilinx: Add FDDRCPE and FDDRRSE blackbox cells.	Marcelina Kościelnicka	2020-12-17	2	-0/+33
\|/ \| \| \| \|	These are necessary primitives for proper DDR support on Virtex 2 and Spartan 3.
*	nexus: More efficient CO mapping	David Shah	2020-12-02	1	-2/+2
\| \| \| \|	Signed-off-by: David Shah <dave@ds0.me>
*	add -noalu and -json option for apicula	Pepijn de Vos	2020-11-30	1	-3/+32
\|
*	nexus: DSP inference support	David Shah	2020-11-20	3	-1/+117
\| \| \| \|	Signed-off-by: David Shah <dave@ds0.me>
*	Merge pull request #2441 from YosysHQ/dave/nexus_dsp_sim	Miodrag Milanović	2020-11-18	3	-250/+573
\|\ \| \| \| \|	nexus: Add DSP simulation model
\| *	nexus: Add DSP simulation model	David Shah	2020-11-18	3	-250/+573
\| \| \| \| \| \| \| \|	Signed-off-by: David Shah <dave@ds0.me>
*	Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes	clairexen	2020-08-20	1	-67/+35
\|\ \| \| \| \|	techmap/shift_shiftx: Remove the "shiftx2mux" special path.
\| *	techmap/shift_shiftx: Remove the "shiftx2mux" special path.	Marcelina Kościelnicka	2020-08-20	1	-67/+35
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Our techmap rules for $shift and $shiftx cells contained a special path that aimed to decompose the shift LSB-first instead of MSB-first in select cases that come up in pmux lowering. This path was needlessly overcomplicated and contained bugs. Instead of doing that, just switch over the main path to iterate LSB-first (except for the specially-handled MSB for signed shifts and overflow handling). This also makes the code consistent with shl/shr/sshl/sshr cells, which are already decomposed LSB-first. Fixes #2346.
* \|	Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern	clairexen	2020-08-20	2	-4/+4
\|\ \ \| \|/ \|/\|	techmap: Add support for [] wildcards in techmap_celltype.
\| *	techmap: Add support for [] wildcards in techmap_celltype.	Marcelina Kościelnicka	2020-08-02	2	-4/+4
\| \| \| \| \| \| \| \|	Fixes #1826.
* \|	Respect \A_SIGNED for $shift	Xiretza	2020-08-18	2	-6/+16
\| \| \| \| \| \| \| \| \| \| \| \|	This reflects the behaviour of $shr/$shl, which sign-extend their A operands to the size of their output, then do a logical shift (shift in 0-bits).
* \|	intel_alm: fix typo in MISTRAL_MUL27X27 cell name	Dan Ravensloft	2020-08-13	1	-1/+1
\| \|
* \|	intel_alm: add more megafunctions. NFC.	Dan Ravensloft	2020-08-12	1	-0/+431
\| \|
* \|	Replace opt_rmdff with opt_dff.	Marcelina Kościelnicka	2020-08-07	7	-29/+26
\|/
*	opt_expr: Remove -clkinv option, make it the default.	Marcelina Kościelnicka	2020-07-31	2	-2/+2
\| \| \| \| \|	Adds -noclkinv option just in case the old behavior was actually useful to someone.
*	synth_ice40: Use opt_dff.	Marcelina Kościelnicka	2020-07-30	4	-142/+6
\| \| \| \| \| \| \| \| \|	The main part is converting ice40_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the mux patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
*	synth_xilinx: Use opt_dff.	Marcelina Kościelnicka	2020-07-30	1	-17/+12
\| \| \| \| \| \| \| \| \|	The main part is converting xilinx_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.