iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Do not require changes to cells_sim.v; try and work out comb model	Eddie Hung	2019-10-05	4	-230/+200
*	abc -> abc9	Eddie Hung	2019-10-04	1	-3/+3
*	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-10-04	4	-181/+9
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\| *	Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`	Eddie Hung	2019-10-04	1	-2/+6
\| *	Remove DSP48E1 from *_cells_xtra.v	Eddie Hung	2019-10-04	3	-178/+2
* \|	Use read_args for read_verilog	Eddie Hung	2019-10-04	1	-3/+6
* \|	Fix merge issues	Eddie Hung	2019-10-04	2	-9/+10
* \|	Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff	Eddie Hung	2019-10-04	31	-278/+294
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\| * \|	Rename abc_* names/attributes to more precisely be abc9_*	Eddie Hung	2019-10-04	31	-227/+235
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\| *	Panic over. Model was elsewhere. Re-arrange for consistency	Eddie Hung	2019-10-04	5	-31/+4
\| *	Oops	Eddie Hung	2019-10-04	1	-1/+1
\| *	Ohmilord this wasn't added all this time!?!	Eddie Hung	2019-10-04	1	-0/+29
* \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-10-03	6	-2/+184
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\| *	ecp5: Fix shuffle_enable port	David Shah	2019-10-01	1	-2/+2
\| *	ecp5: Add support for mapping 36-bit wide PDP BRAMs	David Shah	2019-10-01	6	-1/+183
* \|	English	Eddie Hung	2019-10-03	1	-3/+3
* \|	More fixes	Eddie Hung	2019-10-01	1	-16/+16
* \|	Escape Verilog identifiers for legality outside of Yosys	Eddie Hung	2019-10-01	1	-48/+48
* \|	Remove need for $currQ port connection	Eddie Hung	2019-09-30	2	-111/+118
* \|	Add explanation to abc_map.v	Eddie Hung	2019-09-30	1	-0/+16
* \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-09-30	8	-124/+122
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\| *	Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}	Eddie Hung	2019-09-30	6	-122/+46
\| *	synth_xilinx: Support latches, remove used-up FF init values.	Marcin Kościelnicki	2019-09-30	2	-2/+76
* \|	Missing endmodule	Eddie Hung	2019-09-29	1	-0/+1
* \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-09-29	19	-31/+3401
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\| *	Merge pull request #1359 from YosysHQ/xc7dsp	Eddie Hung	2019-09-29	19	-31/+3395
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\| \| *	Re-order	Eddie Hung	2019-09-27	2	-2/+2
\| \| *	Missing (* mul2dsp *) for sliceB	Eddie Hung	2019-09-27	1	-2/+2
\| \| *	Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once	Eddie Hung	2019-09-26	1	-9/+4
\| \| *	Typo	Eddie Hung	2019-09-26	1	-1/+1
\| \| *	select once	Eddie Hung	2019-09-26	2	-8/+12
\| \| *	Stop trying to be too smart by prematurely optimising	Eddie Hung	2019-09-26	3	-38/+14
\| \| *	mul2dsp.v slice names	Eddie Hung	2019-09-25	1	-5/+5
\| \| *	Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit	Eddie Hung	2019-09-25	1	-3/+1
\| \| *	Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"	Eddie Hung	2019-09-25	1	-2/+6
\| \| *	Revert "No need for $__mul anymore?"	Eddie Hung	2019-09-25	1	-8/+8
\| \| *	Only wreduce on t:$add	Eddie Hung	2019-09-25	1	-1/+1
\| \| *	Remove _TECHMAP_CELLTYPE_ check since all $mul	Eddie Hung	2019-09-25	1	-6/+2
\| \| *	No need for $__mul anymore?	Eddie Hung	2019-09-25	1	-8/+8
\| \| *	Call 'wreduce' after mul2dsp to avoid unextend()	Eddie Hung	2019-09-25	1	-0/+1
\| \| *	Oops. Actually use __NAME__ in ABC_DSP48E1 macro	Eddie Hung	2019-09-25	1	-1/+1
\| \| *	Add (* techmap_autopurge *) to abc_unmap.v too	Eddie Hung	2019-09-23	1	-11/+11
\| \| *	Add techmap_autopurge to outputs in abc_map.v too	Eddie Hung	2019-09-23	1	-11/+11
\| \| *	Revert "Add a xilinx_finalise pass"	Eddie Hung	2019-09-23	3	-87/+0
\| \| *	Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"	Eddie Hung	2019-09-23	1	-38/+38
\| \| *	Revert "Vivado does not like zero width port connections"	Eddie Hung	2019-09-23	1	-2/+2
\| \| *	Vivado does not like zero width port connections	Eddie Hung	2019-09-23	1	-2/+2
\| \| *	Remove (* techmap_autopurge *) from abc_unmap.v since no effect	Eddie Hung	2019-09-23	1	-38/+38
\| \| *	Add a xilinx_finalise pass	Eddie Hung	2019-09-23	3	-0/+87
\| \| *	Grammar	Eddie Hung	2019-09-20	1	-1/+1