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authorEddie Hung <eddie@fpgeh.com>2019-10-03 10:11:25 -0700
committerEddie Hung <eddie@fpgeh.com>2019-10-03 10:11:25 -0700
commit655f1b2ac559f73a7d781ae25afd1ab3b898afc0 (patch)
treee4f48350cd7286922e8ac9ac643c3f5c40df1bd3 /techlibs
parent5299884f049e73c395fdff090b345b15d54aab1e (diff)
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-rw-r--r--techlibs/xilinx/abc_map.v6
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 4eec77df9..db996fbc3 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -29,11 +29,11 @@
// ============================================================================
// The purpose of the following FD* rules are to wrap the flop (which, when
-// called with the `_ABC' macro set captures contains only its combinatorial
+// called with the `_ABC' macro set captures only its combinatorial
// behaviour) with:
// (a) a special $__ABC_FF_ in front of the FD*'s output, indicating to abc9
-// the location of its basic D-Q flop
-// (b) a special TECHMAP_REPLACE_.$currQwire that will be used for feedback
+// the connectivity of its basic D-Q flop
+// (b) a special TECHMAP_REPLACE_.$currQ wire that will be used for feedback
// into the (combinatorial) FD* cell to facilitate clock-enable behaviour
module FDRE (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;