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Author
Age
Files
Lines
*
Using "via_celltype" in $mul carry-save-acc implementation
Clifford Wolf
2014-08-18
1
-34
/
+72
*
Performance fix for new $__lcu techmap rule
Clifford Wolf
2014-08-18
1
-7
/
+5
*
Replaced recursive lcu scheme with bk adder
Clifford Wolf
2014-08-18
1
-61
/
+31
*
Multiply using a carry-save accumulator
Clifford Wolf
2014-08-16
1
-5
/
+45
*
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...
Clifford Wolf
2014-08-16
1
-0
/
+42
*
Changes in techmap $__alu interface
Clifford Wolf
2014-08-16
1
-17
/
+17
*
Renamed $lut ports to follow A-Y naming scheme
Clifford Wolf
2014-08-15
2
-29
/
+29
*
Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
2
-3
/
+3
*
Simplified $__arraymul techmap rule
Clifford Wolf
2014-08-14
1
-7
/
+13
*
RIP $safe_pmux
Clifford Wolf
2014-08-14
2
-64
/
+4
*
Added techmap support for actual lookahead carry unit
Clifford Wolf
2014-08-13
1
-22
/
+73
*
Preparations for lookahead ALU support in techmap.v
Clifford Wolf
2014-08-13
1
-28
/
+92
*
New interface for $__alu in techmap.v
Clifford Wolf
2014-08-13
1
-129
/
+62
*
Added adff2dff.v (for techmap -share_map)
Clifford Wolf
2014-08-07
2
-1
/
+32
*
Implemented recursive techmap
Clifford Wolf
2014-08-03
1
-1
/
+1
*
Renamed "stdcells.v" to "techmap.v"
Clifford Wolf
2014-07-31
3
-2
/
+6
*
Reorganized stdcells.v (no actual code change, just moved and indented stuff)
Clifford Wolf
2014-07-31
1
-747
/
+590
*
Added techmap CONSTMAP feature
Clifford Wolf
2014-07-30
1
-2
/
+4
*
New techmap default rules for $shr $sshr $shl $sshl
Clifford Wolf
2014-07-30
1
-282
/
+62
*
Bugfix in simlib.v for iverilog
Clifford Wolf
2014-07-29
1
-5
/
+6
*
Added $shift and $shiftx cell types (needed for correct part select behavior)
Clifford Wolf
2014-07-29
2
-8
/
+112
*
Added "make PRETTY=1"
Clifford Wolf
2014-07-24
2
-12
/
+12
*
Fixed simlib.v model for $mem
Clifford Wolf
2014-07-17
1
-15
/
+15
*
Updated simlib to new $mem/$memwr interface
Clifford Wolf
2014-07-16
1
-30
/
+55
*
Added SIMLIB_NOLUT to simlib.v
Clifford Wolf
2014-04-02
1
-0
/
+2
*
Added SIMLIB_NOSR to simlib.v
Clifford Wolf
2014-04-02
1
-0
/
+6
*
Added support for dlatchsr cells
Clifford Wolf
2014-03-31
2
-0
/
+136
*
Merged addition of SED makefile variable from github.com/Siesh1oo/yosys
Clifford Wolf
2014-03-11
1
-1
/
+1
*
Fixes for improved techmap of shifts with large B inputs
Clifford Wolf
2014-03-06
1
-8
/
+8
*
Strictly zero-extend unsigned A-inputs of shift operations in techmap
Clifford Wolf
2014-03-06
1
-4
/
+4
*
Improved techmap of shift with wide B inputs
Clifford Wolf
2014-03-06
1
-13
/
+37
*
Added $slice and $concat cell types
Clifford Wolf
2014-02-07
2
-0
/
+42
*
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf
2014-02-03
1
-13
/
+47
*
More changes to techlibs/common/simlib.v for LEC
Clifford Wolf
2014-01-31
1
-6
/
+11
*
Added test comments to techlibs/cmos/cmos_cells.lib
Clifford Wolf
2014-01-29
1
-0
/
+2
*
Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)
Clifford Wolf
2014-01-29
1
-105
/
+305
*
Added $assert cell
Clifford Wolf
2014-01-19
1
-0
/
+15
*
Fixed $lut simlib model for a wider range of tools
Clifford Wolf
2014-01-18
1
-10
/
+12
*
More changes to simlib to make it friendlier to a wider range of tools
Clifford Wolf
2014-01-18
1
-10
/
+14
*
Fixed a type in $mem model in simlib.v
Clifford Wolf
2014-01-18
1
-1
/
+1
*
Removed cases of trailing comma in stdcells.v
Clifford Wolf
2014-01-18
1
-3
/
+3
*
Added $bu0 cell to simlib.v
Clifford Wolf
2014-01-18
1
-0
/
+22
*
Added techlibs/common/pmux2mux.v
Clifford Wolf
2014-01-17
2
-1
/
+26
*
Various small cleanups in stdcells.v techmap code
Clifford Wolf
2013-12-31
1
-68
/
+38
*
Added $bu0 cell (for easy correct $eq/$ne mapping)
Clifford Wolf
2013-12-28
1
-4
/
+10
*
Added support for non-const === and !== (for miter circuits)
Clifford Wolf
2013-12-27
2
-0
/
+86
*
Using simplemap mappers from techmap
Clifford Wolf
2013-11-24
1
-714
/
+40
*
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
Clifford Wolf
2013-11-24
4
-20
/
+23
*
Added "techmap -share_map" option
Clifford Wolf
2013-11-24
1
-4
/
+4
*
Fixed xilinx/example_sim_counter test bench
Clifford Wolf
2013-11-24
1
-1
/
+1
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