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| | * | | abc9_ops: generate flop box ids, add abc9_required to FD* cellsEddie Hung2020-01-141-12/+45
| | * | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_req...Eddie Hung2020-01-143-23/+30
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| | * \ \ \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_req...Eddie Hung2020-01-122-3/+2
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| | * | | | | Add abc9_required to DSP48E1.{A,B,C,D,PCIN}Eddie Hung2020-01-101-38/+117
| | * | | | | abc9_ops -prep_times: generate flop boxes from abc9_required attrEddie Hung2020-01-101-61/+0
| | * | | | | Add abc9_ops -check, -prep_times, -write_box for required timesEddie Hung2020-01-101-0/+5
| | * | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_req...Eddie Hung2020-01-086-1676/+520
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| | * \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_r...Eddie Hung2020-01-0639-656/+1189
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| | | * \ \ \ \ \ Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactorEddie Hung2020-01-0212-756/+722
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| | | * \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-0227-91/+118
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| | | * \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactorEddie Hung2019-12-306-121/+673
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| | * | | | | | | | | | ConsistencyEddie Hung2019-12-271-1/+1
| | * | | | | | | | | | Update some abc9_arrival times, add abc9_required timesEddie Hung2019-12-273-24/+220
| * | | | | | | | | | | Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-033-0/+3
| * | | | | | | | | | | xilinx: use RAM32M/RAM64M for memories with two read portsMarcin Kościelnicki2020-02-021-2/+2
| * | | | | | | | | | | Merge pull request #1659 from YosysHQ/clifford/experimentalClaire Wolf2020-01-291-1/+1
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| | * | | | | | | | | | | Add log_experimental() and experimental() API and "yosys -x"Claire Wolf2020-01-271-1/+1
| * | | | | | | | | | | | synth_xilinx: cleanup helpEddie Hung2020-01-281-6/+4
| * | | | | | | | | | | | synth_xilinx: fix help when no active_design; fixes #1664Eddie Hung2020-01-281-2/+3
| * | | | | | | | | | | | xilinx: Add simulation model for DSP48 (Virtex 4).Marcin Kościelnicki2020-01-296-45/+534
| * | | | | | | | | | | | Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_lutsEddie Hung2020-01-284-148/+100
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| | * | | | | | | | | | | | Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwardsEddie Hung2020-01-271-1/+1
| | * | | | | | | | | | | | Import tests from #1628Eddie Hung2020-01-271-2/+2
| | * | | | | | | | | | | | xilinx/ice40/ecp5: undo permuting LUT masks in lut_mapEddie Hung2020-01-273-146/+98
| * | | | | | | | | | | | | Fix unresolved conflict from #1573Eddie Hung2020-01-281-1/+1
| * | | | | | | | | | | | | Merge pull request #1573 from YosysHQ/eddie/xilinx_tristateN. Engelhardt2020-01-281-0/+3
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| | * | | | | | | | | | | | Duplicate tribuf call, credit to @mwkmwkmwkEddie Hung2019-12-131-1/+0
| | * | | | | | | | | | | | synth_xilinx: error out if tristate without '-iopad'Eddie Hung2019-12-121-0/+4
| * | | | | | | | | | | | | Merge pull request #1619 from YosysHQ/eddie/abc9_refactorEddie Hung2020-01-271-8/+8
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| | * | | | | | | | | | | | Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0Eddie Hung2020-01-221-1/+1
| | * | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-214-128/+98
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| | * | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-151-1/+1
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| | * | | | | | | | | | | | Adding (* techmap_autopurge *) to FD* in abc9_map.vEddie Hung2020-01-141-8/+8
| * | | | | | | | | | | | | Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warningsEddie Hung2020-01-274-6/+10
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| | * | | | | | | | | | | | ice40: reduce ABC9 internal fanout warnings with a param for CI->I3Eddie Hung2020-01-244-6/+10
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| * | | | | | | | | | | | ice40: add SB_SPRAM256KA arrival timeEddie Hung2020-01-241-0/+1
| * | | | | | | | | | | | Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0Eddie Hung2020-01-231-1/+1
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* | | | | | | | | | | | Explicitly create separate $mux cellsEddie Hung2020-01-211-2/+2
* | | | | | | | | | | | Fix tests -- when Y_WIDTH is non-pow-2Eddie Hung2020-01-211-3/+4
* | | | | | | | | | | | Move from +/shiftx2mux.v into +/techmap.v; cleanupEddie Hung2020-01-213-73/+69
* | | | | | | | | | | | New techmap +/shiftx2mux.v which decomposes LSB first; better for ABCEddie Hung2020-01-212-0/+39
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* | | | | | | | | | | Merge pull request #1643 from YosysHQ/eddie/cleanup_arith_mapEddie Hung2020-01-182-125/+88
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| * | | | | | | | | | | Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623Eddie Hung2020-01-172-119/+82
| * | | | | | | | | | | +/xilinx/arith_map.v fix $lcu ruleEddie Hung2020-01-171-6/+6
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* | | | | | | | | | | Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warningDavid Shah2020-01-181-2/+8
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| * | | | | | | | | | | ice40: Demote conflicting FF init values to a warningNiklas Nisbeth2019-12-311-2/+8
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* | | | | | | | | | | synth_ice40: call wreduce before mul2dspEddie Hung2020-01-171-1/+2
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* | | | | | | | | | Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_WMiodrag Milanović2020-01-151-1/+1
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| * | | | | | | | | synth_xilinx: fix default W value for non-xc7Eddie Hung2020-01-141-1/+1
* | | | | | | | | | Merge pull request #1623 from YosysHQ/mmicko/edif_attrMiodrag Milanović2020-01-141-1/+1
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