Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor

27 files changed, 118 insertions, 91 deletions

diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc
index 626860d9c..1dc6bdb2f 100755
--- a/techlibs/achronix/synth_achronix.cc
+++ b/techlibs/achronix/synth_achronix.cc
@@ -52,7 +52,7 @@ struct SynthAchronixPass : public ScriptPass {
     log("        do not flatten design before synthesis\n");
     log("\n");
     log("    -retime\n");
-    log("        run 'abc' with -dff option\n");
+    log("        run 'abc' with '-dff -D 1' options\n");
     log("\n");
     log("\n");
     log("The following commands are executed by this synthesis command:\n");
@@ -152,12 +152,12 @@ struct SynthAchronixPass : public ScriptPass {
         run("clean -purge");
         run("setundef -undriven -zero");
         if (retime || help_mode)
-          run("abc -markgroups -dff", "(only if -retime)");
+          run("abc -markgroups -dff -D 1", "(only if -retime)");
       }
 
     if (check_label("map_luts"))
       {
-        run("abc -lut 4" + string(retime ? " -dff" : ""));
+        run("abc -lut 4" + string(retime ? " -dff -D 1" : ""));
         run("clean");
       }
 
diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc
index 9426b5ca5..2d8d65e2e 100644
--- a/techlibs/anlogic/Makefile.inc
+++ b/techlibs/anlogic/Makefile.inc
@@ -7,6 +7,6 @@ $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
-$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt))
-$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v))
-$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/dram_init_16x4.vh))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams.txt))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams_map.v))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutram_init_16x4.vh))
diff --git a/techlibs/anlogic/cells_map.v b/techlibs/anlogic/cells_map.v
index cfc743a4b..8ac087d9d 100644
--- a/techlibs/anlogic/cells_map.v
+++ b/techlibs/anlogic/cells_map.v
@@ -6,14 +6,14 @@ module  \$_DFFE_NP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REG
 module  \$_DFFE_PN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(E), .sr(1'b0)); endmodule
 module  \$_DFFE_PP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(E), .sr(1'b0)); endmodule
 
-module  \$_DFF_NN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_NN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_NP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_NP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_PN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) , .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_NN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_NN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_NP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"),  .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_NP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"),  .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) , .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"),  .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
 
 module \$_DLATCH_N_ (E, D, Q);
   wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
diff --git a/techlibs/anlogic/dram_init_16x4.vh b/techlibs/anlogic/lutram_init_16x4.vh
index 32fb1578c..32fb1578c 100644
--- a/techlibs/anlogic/dram_init_16x4.vh
+++ b/techlibs/anlogic/lutram_init_16x4.vh
diff --git a/techlibs/anlogic/drams.txt b/techlibs/anlogic/lutrams.txt
index 4e903c0a2..4e903c0a2 100644
--- a/techlibs/anlogic/drams.txt
+++ b/techlibs/anlogic/lutrams.txt
diff --git a/techlibs/anlogic/drams_map.v b/techlibs/anlogic/lutrams_map.v
index 084e2a25f..5a464cafc 100644
--- a/techlibs/anlogic/drams_map.v
+++ b/techlibs/anlogic/lutrams_map.v
@@ -10,7 +10,7 @@ module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 	input B1EN;
 
 	EG_LOGIC_DRAM16X4 #(
-		`include "dram_init_16x4.vh"
+		`include "lutram_init_16x4.vh"
 	) _TECHMAP_REPLACE_ (
 		.di(B1DATA),
 		.waddr(B1ADDR),
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index b87fc8566..aaa6bda4a 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -58,7 +58,10 @@ struct SynthAnlogicPass : public ScriptPass
 		log("        do not flatten design before synthesis\n");
 		log("\n");
 		log("    -retime\n");
-		log("        run 'abc' with -dff option\n");
+		log("        run 'abc' with '-dff -D 1' options\n");
+		log("\n");
+		log("    -nolutram\n");
+		log("        do not use EG_LOGIC_DRAM16X4 cells in output netlist\n");
 		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
@@ -67,7 +70,7 @@ struct SynthAnlogicPass : public ScriptPass
 	}
 
 	string top_opt, edif_file, json_file;
-	bool flatten, retime;
+	bool flatten, retime, nolutram;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -76,6 +79,7 @@ struct SynthAnlogicPass : public ScriptPass
 		json_file = "";
 		flatten = true;
 		retime = false;
+		nolutram = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -110,6 +114,10 @@ struct SynthAnlogicPass : public ScriptPass
 				flatten = false;
 				continue;
 			}
+			if (args[argidx] == "-nolutram") {
+				nolutram = true;
+				continue;
+			}
 			if (args[argidx] == "-retime") {
 				retime = true;
 				continue;
@@ -150,21 +158,25 @@ struct SynthAnlogicPass : public ScriptPass
 			run("synth -run coarse");
 		}
 
-		if (check_label("dram"))
+		if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
 		{
-			run("memory_bram -rules +/anlogic/drams.txt");
-			run("techmap -map +/anlogic/drams_map.v");
+			run("memory_bram -rules +/anlogic/lutrams.txt");
+			run("techmap -map +/anlogic/lutrams_map.v");
 			run("setundef -zero -params t:EG_LOGIC_DRAM16X4");
 		}
 
-		if (check_label("fine"))
+		if (check_label("map_ffram"))
 		{
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
 			run("opt -undriven -fine");
+		}
+
+		if (check_label("map_gates"))
+		{
 			run("techmap -map +/techmap.v -map +/anlogic/arith_map.v");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run("abc -dff -D 1", "(only if -retime)");
 		}
 
 		if (check_label("map_ffs"))
@@ -187,7 +199,7 @@ struct SynthAnlogicPass : public ScriptPass
 			run("techmap -map +/anlogic/cells_map.v");
 			run("clean");
 		}
-		
+
 		if (check_label("map_anlogic"))
 		{
 			run("anlogic_fixcarry");
diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc
index 014c68622..388e2b792 100644
--- a/techlibs/coolrunner2/synth_coolrunner2.cc
+++ b/techlibs/coolrunner2/synth_coolrunner2.cc
@@ -55,7 +55,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
 		log("        do not flatten design before synthesis\n");
 		log("\n");
 		log("    -retime\n");
-		log("        run 'abc' with -dff option\n");
+		log("        run 'abc' with '-dff -D 1' options\n");
 		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
@@ -161,7 +161,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
 
 		if (check_label("map_pla"))
 		{
-			run("abc -sop -I 40 -P 56");
+			run("abc -sop -I 40 -P 56" + string(retime ? " -dff -D 1" : ""));
 			run("clean");
 		}
 
diff --git a/techlibs/easic/synth_easic.cc b/techlibs/easic/synth_easic.cc
index dd9e3dab7..b4a3a1ac9 100644
--- a/techlibs/easic/synth_easic.cc
+++ b/techlibs/easic/synth_easic.cc
@@ -56,7 +56,7 @@ struct SynthEasicPass : public ScriptPass
 		log("        do not flatten design before synthesis\n");
 		log("\n");
 		log("    -retime\n");
-		log("        run 'abc' with -dff option\n");
+		log("        run 'abc' with '-dff -D 1' options\n");
 		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
@@ -158,7 +158,7 @@ struct SynthEasicPass : public ScriptPass
 			run("techmap");
 			run("opt -fast");
 			if (retime || help_mode) {
-				run("abc -dff", " (only if -retime)");
+				run("abc -dff -D 1", " (only if -retime)");
 				run("opt_clean", "(only if -retime)");
 			}
 		}
diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 46463f510..2c33f23b9 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -8,9 +8,9 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams_map.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
diff --git a/techlibs/ecp5/bram.txt b/techlibs/ecp5/brams.txt
index 777ccaa2e..777ccaa2e 100644
--- a/techlibs/ecp5/bram.txt
+++ b/techlibs/ecp5/brams.txt
diff --git a/techlibs/ecp5/lutram.txt b/techlibs/ecp5/lutrams.txt
index b94357429..b94357429 100644
--- a/techlibs/ecp5/lutram.txt
+++ b/techlibs/ecp5/lutrams.txt
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index a0ea6d1f9..d616391b2 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -62,7 +62,7 @@ struct SynthEcp5Pass : public ScriptPass
 		log("        do not flatten design before synthesis\n");
 		log("\n");
 		log("    -retime\n");
-		log("        run 'abc' with -dff option\n");
+		log("        run 'abc' with '-dff -D 1' options\n");
 		log("\n");
 		log("    -noccu2\n");
 		log("        do not use CCU2 cells in output netlist\n");
@@ -266,13 +266,13 @@ struct SynthEcp5Pass : public ScriptPass
 
 		if (!nobram && check_label("map_bram", "(skip if -nobram)"))
 		{
-			run("memory_bram -rules +/ecp5/bram.txt");
+			run("memory_bram -rules +/ecp5/brams.txt");
 			run("techmap -map +/ecp5/brams_map.v");
 		}
 
 		if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
 		{
-			run("memory_bram -rules +/ecp5/lutram.txt");
+			run("memory_bram -rules +/ecp5/lutrams.txt");
 			run("techmap -map +/ecp5/lutrams_map.v");
 		}
 
@@ -290,7 +290,7 @@ struct SynthEcp5Pass : public ScriptPass
 			else
 				run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run("abc -dff -D 1", "(only if -retime)");
 		}
 
 		if (check_label("map_ffs"))
diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc
index 5013f7fc1..69665982c 100644
--- a/techlibs/efinix/Makefile.inc
+++ b/techlibs/efinix/Makefile.inc
@@ -7,4 +7,4 @@ $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v))
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v))
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v))
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/brams_map.v))
-$(eval $(call add_share_file,share/efinix,techlibs/efinix/bram.txt))
+$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams.txt))
diff --git a/techlibs/efinix/bram.txt b/techlibs/efinix/brams.txt
index 0b3fd9308..0b3fd9308 100644
--- a/techlibs/efinix/bram.txt
+++ b/techlibs/efinix/brams.txt
diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc
index 26a8d4eda..0efd91708 100644
--- a/techlibs/efinix/synth_efinix.cc
+++ b/techlibs/efinix/synth_efinix.cc
@@ -58,7 +58,10 @@ struct SynthEfinixPass : public ScriptPass
 		log("        do not flatten design before synthesis\n");
 		log("\n");
 		log("    -retime\n");
-		log("        run 'abc' with -dff option\n");
+		log("        run 'abc' with '-dff -D 1' options\n");
+		log("\n");
+		log("    -nobram\n");
+		log("        do not use EFX_RAM_5K cells in output netlist\n");
 		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
@@ -67,7 +70,7 @@ struct SynthEfinixPass : public ScriptPass
 	}
 
 	string top_opt, edif_file, json_file;
-	bool flatten, retime;
+	bool flatten, retime, nobram;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -76,6 +79,7 @@ struct SynthEfinixPass : public ScriptPass
 		json_file = "";
 		flatten = true;
 		retime = false;
+		nobram = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -114,6 +118,10 @@ struct SynthEfinixPass : public ScriptPass
 				retime = true;
 				continue;
 			}
+			if (args[argidx] == "-nobram") {
+				nobram = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -150,21 +158,25 @@ struct SynthEfinixPass : public ScriptPass
 			run("synth -run coarse");
 		}
 
-		if (check_label("map_bram", "(skip if -nobram)"))
+		if (!nobram || check_label("map_bram", "(skip if -nobram)"))
 		{
-			run("memory_bram -rules +/efinix/bram.txt");
+			run("memory_bram -rules +/efinix/brams.txt");
 			run("techmap -map +/efinix/brams_map.v");
 			run("setundef -zero -params t:EFX_RAM_5K");
 		}
 
-		if (check_label("fine"))
+		if (check_label("map_ffram"))
 		{
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
 			run("opt -undriven -fine");
+		}
+
+		if (check_label("map_gates"))
+		{
 			run("techmap -map +/techmap.v -map +/efinix/arith_map.v");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run("abc -dff -D 1", "(only if -retime)");
 		}
 
 		if (check_label("map_ffs"))
@@ -194,7 +206,7 @@ struct SynthEfinixPass : public ScriptPass
 			run("efinix_fixcarry");
 			run("clean");
 		}
-		
+
 		if (check_label("check"))
 		{
 			run("hierarchy -check");
diff --git a/techlibs/gowin/Makefile.inc b/techlibs/gowin/Makefile.inc
index d2853704b..fe5d9d6e6 100644
--- a/techlibs/gowin/Makefile.inc
+++ b/techlibs/gowin/Makefile.inc
@@ -7,9 +7,9 @@ $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v))
 $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v))
 $(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v))
 $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map.v))
-$(eval $(call add_share_file,share/gowin,techlibs/gowin/bram.txt))
-$(eval $(call add_share_file,share/gowin,techlibs/gowin/drams_map.v))
-$(eval $(call add_share_file,share/gowin,techlibs/gowin/dram.txt))
+$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt))
+$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams_map.v))
+$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams.txt))
 
 
 
diff --git a/techlibs/gowin/bram.txt b/techlibs/gowin/brams.txt
index e406f9c51..e406f9c51 100644
--- a/techlibs/gowin/bram.txt
+++ b/techlibs/gowin/brams.txt
diff --git a/techlibs/gowin/dram.txt b/techlibs/gowin/lutrams.txt
index 9db530251..9db530251 100644
--- a/techlibs/gowin/dram.txt
+++ b/techlibs/gowin/lutrams.txt
diff --git a/techlibs/gowin/drams_map.v b/techlibs/gowin/lutrams_map.v
index a50ab365a..a50ab365a 100644
--- a/techlibs/gowin/drams_map.v
+++ b/techlibs/gowin/lutrams_map.v
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 6cf058f29..c5b41b503 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -55,23 +55,23 @@ struct SynthGowinPass : public ScriptPass
 		log("    -nobram\n");
 		log("        do not use BRAM cells in output netlist\n");
 		log("\n");
-		log("    -nodram\n");
+		log("    -nolutram\n");
 		log("        do not use distributed RAM cells in output netlist\n");
 		log("\n");
 		log("    -noflatten\n");
 		log("        do not flatten design before synthesis\n");
 		log("\n");
 		log("    -retime\n");
-		log("        run 'abc' with -dff option\n");
+		log("        run 'abc' with '-dff -D 1' options\n");
 		log("\n");
 		log("    -nowidelut\n");
 		log("        do not use muxes to implement LUTs larger than LUT4s\n");
 		log("\n");
 		log("    -noiopads\n");
 		log("        do not emit IOB at top level ports\n");
-		log("\n");
-		log("    -abc9\n");
-		log("        use new ABC9 flow (EXPERIMENTAL)\n");
+		//log("\n");
+		//log("    -abc9\n");
+		//log("        use new ABC9 flow (EXPERIMENTAL)\n");
 		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
@@ -80,7 +80,7 @@ struct SynthGowinPass : public ScriptPass
 	}
 
 	string top_opt, vout_file;
-	bool retime, nobram, nodram, flatten, nodffe, nowidelut, abc9, noiopads;
+	bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -90,7 +90,7 @@ struct SynthGowinPass : public ScriptPass
 		flatten = true;
 		nobram = false;
 		nodffe = false;
-		nodram = false;
+		nolutram = false;
 		nowidelut = false;
 		abc9 = false;
 		noiopads = false;
@@ -128,8 +128,8 @@ struct SynthGowinPass : public ScriptPass
 				nobram = true;
 				continue;
 			}
-			if (args[argidx] == "-nodram") {
-				nodram = true;
+			if (args[argidx] == "-nolutram" || /*deprecated*/args[argidx] == "-nodram") {
+				nolutram = true;
 				continue;
 			}
 			if (args[argidx] == "-nodffe") {
@@ -144,10 +144,10 @@ struct SynthGowinPass : public ScriptPass
 				nowidelut = true;
 				continue;
 			}
-			if (args[argidx] == "-abc9") {
-				abc9 = true;
-				continue;
-			}
+			//if (args[argidx] == "-abc9") {
+			//	abc9 = true;
+			//	continue;
+			//}
 			if (args[argidx] == "-noiopads") {
 				noiopads = true;
 				continue;
@@ -188,28 +188,32 @@ struct SynthGowinPass : public ScriptPass
 			run("synth -run coarse");
 		}
 
-		if (!nobram && check_label("bram", "(skip if -nobram)"))
+		if (!nobram && check_label("map_bram", "(skip if -nobram)"))
 		{
-			run("memory_bram -rules +/gowin/bram.txt");
+			run("memory_bram -rules +/gowin/brams.txt");
 			run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
 		}
 
-		if (!nodram && check_label("dram", "(skip if -nodram)"))
+		if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
 		{
-			run("memory_bram -rules +/gowin/dram.txt");
-			run("techmap -map +/gowin/drams_map.v");
+			run("memory_bram -rules +/gowin/lutrams.txt");
+			run("techmap -map +/gowin/lutrams_map.v");
 			run("determine_init");
 		}
 
-		if (check_label("fine"))
+		if (check_label("map_ffram"))
 		{
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
 			run("opt -undriven -fine");
+		}
+
+		if (check_label("map_gates"))
+		{
 			run("techmap -map +/techmap.v -map +/gowin/arith_map.v");
 			run("techmap -map +/techmap.v");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run("abc -dff -D 1", "(only if -retime)");
 			run("splitnets");
 		}
 
@@ -227,13 +231,13 @@ struct SynthGowinPass : public ScriptPass
 
 		if (check_label("map_luts"))
 		{
-			if (nowidelut && abc9) {
+			/*if (nowidelut && abc9) {
 				run("abc9 -lut 4");
-			} else if (nowidelut && !abc9) {
+			} else*/ if (nowidelut && !abc9) {
 				run("abc -lut 4");
-			} else if (!nowidelut && abc9) {
+			} else /*if (!nowidelut && abc9) {
 				run("abc9 -lut 4:8");
-			} else if (!nowidelut && !abc9) {
+			} else*/ if (!nowidelut && !abc9) {
 				run("abc -lut 4:8");
 			}
 			run("clean");
@@ -248,7 +252,6 @@ struct SynthGowinPass : public ScriptPass
 				run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O "
 					"-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)");
 			run("clean");
-
 		}
 
 		if (check_label("check"))
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index eeb001b46..e1fbe6b69 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -59,7 +59,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 		log("        do not flatten design before synthesis\n");
 		log("\n");
 		log("    -retime\n");
-		log("        run 'abc' with -dff option\n");
+		log("        run 'abc' with '-dff -D 1' options\n");
 		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
@@ -165,7 +165,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 			run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
 			run("opt -fast");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run("abc -dff -D 1", "(only if -retime)");
 		}
 
 		if (check_label("map_luts"))
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index ed7a16c08..463c2063a 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -65,7 +65,7 @@ struct SynthIce40Pass : public ScriptPass
 		log("        do not flatten design before synthesis\n");
 		log("\n");
 		log("    -retime\n");
-		log("        run 'abc' with -dff option\n");
+		log("        run 'abc' with '-dff -D 1' options\n");
 		log("\n");
 		log("    -nocarry\n");
 		log("        do not use SB_CARRY cells in output netlist\n");
@@ -316,7 +316,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
 			}
 			if (retime || help_mode)
-				run(abc + " -dff", "(only if -retime)");
+				run(abc + " -dff -D 1", "(only if -retime)");
 			run("ice40_opt");
 		}
 
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index c8c690e45..2ebb8bf50 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -71,7 +71,7 @@ struct SynthIntelPass : public ScriptPass {
 		log("        do not flatten design before synthesis\n");
 		log("\n");
 		log("    -retime\n");
-		log("        run 'abc' with -dff option\n");
+		log("        run 'abc' with '-dff -D 1' options\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
@@ -187,10 +187,10 @@ struct SynthIntelPass : public ScriptPass {
 		}
 
 		if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
-                        if (family_opt == "cycloneiv" ||
-                            family_opt == "cycloneive" ||
-                            family_opt == "max10" ||
-                            help_mode) {
+				if (family_opt == "cycloneiv" ||
+				    family_opt == "cycloneive" ||
+				    family_opt == "max10" ||
+				    help_mode) {
 				run("memory_bram -rules +/intel/common/brams_m9k.txt", "(if applicable for family)");
 				run("techmap -map +/intel/common/brams_map_m9k.v", "(if applicable for family)");
 			} else {
@@ -210,7 +210,7 @@ struct SynthIntelPass : public ScriptPass {
 			run("clean -purge");
 			run("setundef -undriven -zero");
 			if (retime || help_mode)
-				run("abc -markgroups -dff", "(only if -retime)");
+				run("abc -markgroups -dff -D 1", "(only if -retime)");
 		}
 
 		if (check_label("map_luts")) {
@@ -224,7 +224,7 @@ struct SynthIntelPass : public ScriptPass {
 		if (check_label("map_cells")) {
 			if (iopads || help_mode)
 				run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(if -iopads)");
-                        run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
+			run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
 			run("dffinit -highlow -ff dffeas q power_up");
 			run("clean -purge");
 		}
diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc
index 0924df7a6..543dfdb9e 100644
--- a/techlibs/sf2/synth_sf2.cc
+++ b/techlibs/sf2/synth_sf2.cc
@@ -67,7 +67,7 @@ struct SynthSf2Pass : public ScriptPass
 		log("        insert direct PAD->global_net buffers\n");
 		log("\n");
 		log("    -retime\n");
-		log("        run 'abc' with -dff option\n");
+		log("        run 'abc' with '-dff -D 1' options\n");
 		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
@@ -181,7 +181,7 @@ struct SynthSf2Pass : public ScriptPass
 			run("opt -undriven -fine");
 			run("techmap -map +/techmap.v -map +/sf2/arith_map.v");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run("abc -dff -D 1", "(only if -retime)");
 		}
 
 		if (check_label("map_ffs"))
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index b51248d9d..db7242f85 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -2244,7 +2244,7 @@ module DSP48E1 (
     parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
 
     initial begin
-`ifdef __ICARUS__
+`ifndef YOSYS
         if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value");
         if (SEL_MASK != "MASK")     $fatal(1, "Unsupported SEL_MASK value");
         if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value");
@@ -2407,12 +2407,12 @@ module DSP48E1 (
         case (OPMODEr[1:0])
             2'b00: X = 48'b0;
             2'b01: begin X = $signed(Mrx);
-`ifdef __ICARUS__
+`ifndef YOSYS
                 if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01");
 `endif
             end
             2'b10: begin X = P;
-`ifdef __ICARUS__
+`ifndef YOSYS
                 if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10");
 `endif
             end
@@ -2424,7 +2424,7 @@ module DSP48E1 (
         case (OPMODEr[3:2])
             2'b00: Y = 48'b0;
             2'b01: begin Y = 48'b0; // FIXME: more accurate partial product modelling?
-`ifdef __ICARUS__
+`ifndef YOSYS
                 if (OPMODEr[1:0] != 2'b01) $fatal(1, "OPMODEr[1:0] must be 2'b01 when OPMODEr[3:2] is 2'b01");
 `endif
             end
@@ -2438,13 +2438,13 @@ module DSP48E1 (
             3'b000: Z = 48'b0;
             3'b001: Z = PCIN;
             3'b010: begin Z = P;
-`ifdef __ICARUS__
+`ifndef YOSYS
                 if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] i0s 3'b010");
 `endif
             end
             3'b011: Z = Cr;
             3'b100: begin Z = P;
-`ifdef __ICARUS__
+`ifndef YOSYS
                 if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100");
                 if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100");
 `endif
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index f2a9ae982..2f4c503f2 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -111,7 +111,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("        run 'abc9' with -dff option\n");
 		log("\n");
 		log("    -retime\n");
-		log("        run 'abc' with -dff option\n");
+		log("        run 'abc' with '-dff -D 1' options\n");
 		log("\n");
 		log("    -abc9\n");
 		log("        use new ABC9 flow (EXPERIMENTAL)\n");
@@ -564,9 +564,9 @@ struct SynthXilinxPass : public ScriptPass
 			}
 			else {
 				if (nowidelut)
-					run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
+					run("abc -luts 2:2,3,6:5" + string(retime ? " -dff -D 1" : ""));
 				else
-					run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+					run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff -D 1" : ""));
 			}
 			run("clean");