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| author | Claire Wolf <clifford@clifford.at> | 2020-01-27 18:27:47 +0100 |
|---|---|---|
| committer | Claire Wolf <clifford@clifford.at> | 2020-01-27 18:27:47 +0100 |
| commit | cef607c8b77803aa1236d250da4ca6841f78a4ea (patch) | |
| tree | 48e4e7a09e057ab3eb169b3a541ab7df84637250 /techlibs | |
| parent | 07a12ebd4ff12c8016809eacad4551246fa4b316 (diff) | |
| download | yosys-cef607c8b77803aa1236d250da4ca6841f78a4ea.tar.gz yosys-cef607c8b77803aa1236d250da4ca6841f78a4ea.tar.bz2 yosys-cef607c8b77803aa1236d250da4ca6841f78a4ea.zip | |
Add log_experimental() and experimental() API and "yosys -x"
Signed-off-by: Claire Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/intel/synth_intel.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 2ebb8bf50..3689df70e 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -26,7 +26,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct SynthIntelPass : public ScriptPass { - SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") {} + SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { experimental(); } void help() YS_OVERRIDE { |