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| author | Marcin Kościelnicki <mwk@0x04.net> | 2020-02-02 11:26:00 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-02-02 14:34:21 +0100 |
| commit | b44d0e041f09216dd90dccd3f18f146b1dfb7e92 (patch) | |
| tree | 1d15fba3f2ace7f3728a769470f62f64104dc6cc /techlibs | |
| parent | 00fba627118fb536686b3d30f3b81f71b513cd51 (diff) | |
| download | yosys-b44d0e041f09216dd90dccd3f18f146b1dfb7e92.tar.gz yosys-b44d0e041f09216dd90dccd3f18f146b1dfb7e92.tar.bz2 yosys-b44d0e041f09216dd90dccd3f18f146b1dfb7e92.zip | |
xilinx: use RAM32M/RAM64M for memories with two read ports
This fixes inefficient LUT RAM usage for memories with one write
and two read ports (commonly used as register files).
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/lutrams.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt index 29f6b05cc..faf66bc18 100644 --- a/techlibs/xilinx/lutrams.txt +++ b/techlibs/xilinx/lutrams.txt @@ -153,7 +153,7 @@ endmatch match $__XILINX_RAM32X2Q min bits 5 - min rports 3 + min rports 2 min wports 1 make_outreg or_next_if_better @@ -161,7 +161,7 @@ endmatch match $__XILINX_RAM64X1Q min bits 5 - min rports 3 + min rports 2 min wports 1 make_outreg endmatch |