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Author
Age
Files
Lines
*
ALU sim tweaks
Pepijn de Vos
2019-10-24
1
-11
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+11
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add a few more missing dff
Pepijn de Vos
2019-10-21
1
-7
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+16
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add negedge DFF
Pepijn de Vos
2019-10-21
2
-15
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+139
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use ADDSUB ALU mode to remove inverters
Pepijn de Vos
2019-10-21
2
-7
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+77
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Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
Pepijn de Vos
2019-10-21
58
-1315
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+24105
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ecp5: Pass -nomfs to abc9
David Shah
2019-10-20
1
-2
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+2
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Makefile: don't assume python is called `python3`
Sean Cross
2019-10-19
4
-6
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+6
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Merge branch 'master' into mmicko/efinix
Miodrag Milanović
2019-10-18
37
-474
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+305
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ecp5: Add ECLKBRIDGECS blackbox
David Shah
2019-10-11
1
-0
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+7
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ecp5: Add attrmvcp to copy syn_useioff to driving FF
David Shah
2019-10-10
1
-0
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+1
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ecp5: Set syn_useioff on IO FFs to enable packing
David Shah
2019-10-10
1
-8
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+8
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xilinx: Add simulation model for IBUFG.
Marcin Kościelnicki
2019-10-10
5
-33
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+14
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Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
Eddie Hung
2019-10-08
31
-228
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+236
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Merge branch 'master' into eddie/abc_to_abc9
Eddie Hung
2019-10-04
4
-181
/
+9
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Rename abc_* names/attributes to more precisely be abc9_*
Eddie Hung
2019-10-04
31
-227
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+235
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Add comment on why partial multipliers are 18x18
Eddie Hung
2019-10-04
1
-4
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+8
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Fix typo in check_label()
Eddie Hung
2019-10-04
1
-1
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+1
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Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`
Eddie Hung
2019-10-04
1
-2
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+6
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Remove DSP48E1 from *_cells_xtra.v
Eddie Hung
2019-10-04
3
-178
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+2
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Panic over. Model was elsewhere. Re-arrange for consistency
Eddie Hung
2019-10-04
5
-31
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+4
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Oops
Eddie Hung
2019-10-04
1
-1
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+1
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Ohmilord this wasn't added all this time!?!
Eddie Hung
2019-10-04
1
-0
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+29
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FF should be initialized to 0
Miodrag Milanovic
2019-10-04
1
-1
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+3
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Add missing latch mapping
Miodrag Milanovic
2019-10-04
1
-0
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+12
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ecp5: Fix shuffle_enable port
David Shah
2019-10-01
1
-2
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+2
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ecp5: Add support for mapping 36-bit wide PDP BRAMs
David Shah
2019-10-01
6
-1
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+183
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Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
Eddie Hung
2019-09-30
6
-122
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+46
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synth_xilinx: Support latches, remove used-up FF init values.
Marcin Kościelnicki
2019-09-30
2
-2
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+76
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Merge pull request #1359 from YosysHQ/xc7dsp
Eddie Hung
2019-09-29
19
-31
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+3395
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Re-order
Eddie Hung
2019-09-27
2
-2
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+2
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Missing (* mul2dsp *) for sliceB
Eddie Hung
2019-09-27
1
-2
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+2
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Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once
Eddie Hung
2019-09-26
1
-9
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+4
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Typo
Eddie Hung
2019-09-26
1
-1
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+1
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select once
Eddie Hung
2019-09-26
2
-8
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+12
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Stop trying to be too smart by prematurely optimising
Eddie Hung
2019-09-26
3
-38
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+14
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mul2dsp.v slice names
Eddie Hung
2019-09-25
1
-5
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+5
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Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit
Eddie Hung
2019-09-25
1
-3
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+1
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Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"
Eddie Hung
2019-09-25
1
-2
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+6
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Revert "No need for $__mul anymore?"
Eddie Hung
2019-09-25
1
-8
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+8
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Only wreduce on t:$add
Eddie Hung
2019-09-25
1
-1
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+1
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Remove _TECHMAP_CELLTYPE_ check since all $mul
Eddie Hung
2019-09-25
1
-6
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+2
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No need for $__mul anymore?
Eddie Hung
2019-09-25
1
-8
/
+8
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Call 'wreduce' after mul2dsp to avoid unextend()
Eddie Hung
2019-09-25
1
-0
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+1
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Oops. Actually use __NAME__ in ABC_DSP48E1 macro
Eddie Hung
2019-09-25
1
-1
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+1
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Add (* techmap_autopurge *) to abc_unmap.v too
Eddie Hung
2019-09-23
1
-11
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+11
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Add techmap_autopurge to outputs in abc_map.v too
Eddie Hung
2019-09-23
1
-11
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+11
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Revert "Add a xilinx_finalise pass"
Eddie Hung
2019-09-23
3
-87
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+0
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Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"
Eddie Hung
2019-09-23
1
-38
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+38
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Revert "Vivado does not like zero width port connections"
Eddie Hung
2019-09-23
1
-2
/
+2
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Vivado does not like zero width port connections
Eddie Hung
2019-09-23
1
-2
/
+2
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