diff options
| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 13:27:10 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 13:27:10 +0200 |
| commit | 44c3472b9f92e2db855056bff9c0e9549e4cbf3c (patch) | |
| tree | 3e4436a66065c8c084e54a7b49f85af749398993 /techlibs | |
| parent | c0fa6f3e1a001c3cd68c4be3eac877e08fd19971 (diff) | |
| download | yosys-44c3472b9f92e2db855056bff9c0e9549e4cbf3c.tar.gz yosys-44c3472b9f92e2db855056bff9c0e9549e4cbf3c.tar.bz2 yosys-44c3472b9f92e2db855056bff9c0e9549e4cbf3c.zip | |
FF should be initialized to 0
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/efinix/cells_sim.v | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v index 2fc2034a6..a74d1c571 100644 --- a/techlibs/efinix/cells_sim.v +++ b/techlibs/efinix/cells_sim.v @@ -59,7 +59,9 @@ module EFX_FF( assign ce = CE_POLARITY ? CE : ~CE; assign sr = SR_POLARITY ? SR : ~SR; assign d = D_POLARITY ? D : ~D; - + + initial Q = 1'b0; + generate if (SR_SYNC == 1) begin |