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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 12:58:11 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 12:58:11 +0200 |
| commit | 77d557d00b5672eb4c20fe0179c5d706abb43807 (patch) | |
| tree | 8df9f53b528730c3797b500f85f969dde1509465 /techlibs | |
| parent | 2c3e14024637bed14d8e8142f4d05c471630dbf7 (diff) | |
| download | yosys-77d557d00b5672eb4c20fe0179c5d706abb43807.tar.gz yosys-77d557d00b5672eb4c20fe0179c5d706abb43807.tar.bz2 yosys-77d557d00b5672eb4c20fe0179c5d706abb43807.zip | |
Add missing latch mapping
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/efinix/cells_map.v | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/techlibs/efinix/cells_map.v b/techlibs/efinix/cells_map.v index 0aeab1902..3ecec3bac 100644 --- a/techlibs/efinix/cells_map.v +++ b/techlibs/efinix/cells_map.v @@ -17,6 +17,18 @@ module \$_DFF_NP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE module \$_DFF_PP0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule module \$_DFF_PP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule +module \$_DLATCH_N_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = !E ? D : Q; +endmodule + +module \$_DLATCH_P_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = E ? D : Q; +endmodule + `ifndef NO_LUT module \$lut (A, Y); parameter WIDTH = 0; |