aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
Commit message (Collapse)AuthorAgeFilesLines
* Fix port names in SB_IO_ODGraham Edgecombe2017-12-101-18/+18
|
* Remove trailing comma from SB_IO_OD port listGraham Edgecombe2017-12-101-1/+1
| | | | This isn't compatible with Icarus Verilog.
* Fix spelling in -vpr help for synth_ice40Tim Ansell2017-12-081-1/+1
|
* Merge pull request #462 from daveshah1/up5kClifford Wolf2017-11-281-0/+263
|\ | | | | Add remaining UltraPlus cells to ice40 techlib
| * Add remaining UltraPlus cells to ice40 techlibDavid Shah2017-11-281-0/+263
| |
* | Merge pull request #455 from daveshah1/up5kClifford Wolf2017-11-181-0/+103
|\| | | | | Add UltraPlus specific cells to ice40 techlib
| * Remove unnecessary keep attributesDavid Shah2017-11-181-5/+5
| |
| * Merge branch 'master' into up5kDavid Shah2017-11-172-5/+29
| |\
| * | Add some UltraPlus cells to ice40 techlibDavid Shah2017-11-161-0/+103
| | |
* | | Merge pull request #453 from dh73/masterClifford Wolf2017-11-1810-5/+312
|\ \ \ | |_|/ |/| | Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells
| * | Initial Cyclone 10 supportdh732017-11-085-1/+308
| | |
| * | Organizing Speedster file namesdh732017-11-085-4/+4
| |/
* / Add "synth_ice40 -vpr"Clifford Wolf2017-11-162-5/+29
|/
* Clean whitespace and permissions in techlibs/intelLarry Doolittle2017-10-0521-190/+190
|
* Rename "write_verilog -nobasenradix" to "write_verilog -decimal"Clifford Wolf2017-10-031-4/+1
|
* Tested and working altsyncarm without init filesdh732017-10-012-57/+59
|
* Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ↵dh732017-10-0130-727/+2954
| | | | M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
* Add first draft of eASIC back-endClifford Wolf2017-09-292-0/+191
|
* Fix synth_ice40 doc regarding -top defaultClifford Wolf2017-09-291-1/+1
|
* Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.Andrew Zonenberg2017-09-142-2/+4
|
* Initial support for extraction of counters with clock enableAndrew Zonenberg2017-09-141-21/+65
|
* Merge pull request #406 from azonenberg/coolrunner-techmapClifford Wolf2017-09-022-18/+125
|\ | | | | Coolrunner techmapping improvements
| * coolrunner2: Finish fixing special-use p-termsRobert Ou2017-09-011-8/+20
| |
| * coolrunner2: Generate a feed-through AND term when necessaryRobert Ou2017-09-011-13/+31
| |
| * coolrunner2: Initial fixes for special p-termsRobert Ou2017-09-012-1/+81
| | | | | | | | | | Certain signals can only be controlled by a product term and not a sum-of-products. Do the initial work for fixing this.
| * coolrunner2: Fix mapping of flip-flopsRobert Ou2017-09-011-1/+0
| |
| * coolrunner2: Combine some for loops togetherRobert Ou2017-09-011-16/+14
| |
* | Fixed typo in error messageAndrew Zonenberg2017-09-011-1/+1
| |
* | Added blackbox $__COUNT_ cell modelAndrew Zonenberg2017-09-012-0/+18
| |
* | Refactoring: moved modules still in cells_sim to cells_sim_wipAndrew Zonenberg2017-09-013-136/+138
|/
* Merge branch 'master' of https://github.com/cliffordwolf/yosys into ↵Andrew Zonenberg2017-08-301-34/+34
|\ | | | | | | counter-extraction
| * Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're ↵Andrew Zonenberg2017-08-281-34/+34
| | | | | | | | multi-edge-sensitive and getting confused.
* | extract_counter: Minor changes requested to comply with upstream policy, ↵Andrew Zonenberg2017-08-302-4/+4
| | | | | | | | fixed a few typos
* | Finished refactoring counter extraction to be nice and generic. Implemented ↵Andrew Zonenberg2017-08-282-1/+69
| | | | | | | | techmapping from $__COUNT_ to GP_COUNTx cells.
* | Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to ↵Andrew Zonenberg2017-08-283-515/+1
|/ | | | techmap/ since it's going to become a generic pass
* Fixed bug causing GP_SPI model to not synthesizeAndrew Zonenberg2017-08-271-2/+2
|
* Fixed more issues with GreenPAK counter sim modelsAndrew Zonenberg2017-08-151-19/+23
|
* Updated PGEN model to have level triggered reset (matches actual hardware ↵Andrew Zonenberg2017-08-151-4/+4
| | | | behavior
* Fixed bug in GP_COUNTx modelAndrew Zonenberg2017-08-151-7/+12
|
* Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was highAndrew Zonenberg2017-08-151-47/+47
|
* Merge pull request #381 from azonenberg/countfixClifford Wolf2017-08-144-504/+900
|\ | | | | Added better behavioral models for GreenPAK counters. Refactored cells_sim into two files so analog/mixed signal stuff is separate
| * Fixed typo in GP_COUNT8 sim modelAndrew Zonenberg2017-08-141-1/+1
| |
| * Fixed typo in error messageAndrew Zonenberg2017-08-141-1/+1
| |
| * Changed LEVEL resets for GP_COUNTx to be properly synthesizeableAndrew Zonenberg2017-08-141-48/+60
| |
| * Changed LEVEL resets to be edge triggered anywayAndrew Zonenberg2017-08-141-4/+4
| |
| * Added level-triggered reset support to GP_COUNTx simulation modelsAndrew Zonenberg2017-08-141-2/+68
| |
| * Fixed undeclared "count" in GP_COUNT8_ADVAndrew Zonenberg2017-08-141-0/+2
| |
| * Fixed undeclared "count" in GP_COUNT14_ADVAndrew Zonenberg2017-08-141-0/+2
| |
| * Fixed typo in last commitAndrew Zonenberg2017-08-141-3/+3
| |
| * Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock ↵Andrew Zonenberg2017-08-142-37/+293
| | | | | | | | divide, but do everything else.
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-12 20:27:10 +0000