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* | xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.Marcin Kościelnicki2020-02-0711-1/+370
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* | xilinx: Add support for Spartan 3A DSP block RAMs.Marcin Kościelnicki2020-02-073-1/+39
| | | | | | | | Part of #1550
* | Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_mapEddie Hung2020-02-061-109/+43
|\ \ | |/ |/| Fix/cleanup +/xilinx/arith_map.v
| * Fix $lcu -> MUXCY mapping, credit @mwkmwkmwkEddie Hung2020-02-061-4/+5
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| * Fix/cleanup +/xilinx/arith_map.vEddie Hung2020-02-061-111/+44
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* | synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-058-5/+9
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* | shiftx2mux: fix select out of boundsEddie Hung2020-02-051-1/+2
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* Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-0524-359/+1041
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| * Merge pull request #1661 from YosysHQ/eddie/abc9_requiredEddie Hung2020-02-057-144/+375
| |\ | | | | | | abc9: add support for required times
| | * Merge branch 'eddie/abc9_refactor' into eddie/abc9_requiredEddie Hung2020-01-275-129/+99
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| | * \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-151-1/+1
| | |\ \ | | | | | | | | | | | | | | | eddie/abc9_required
| | * | | abc9_ops: -write_box is empty, output a dummy box to prevent ABC errorEddie Hung2020-01-152-2/+0
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| | * | | abc9_ops: generate flop box ids, add abc9_required to FD* cellsEddie Hung2020-01-141-12/+45
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| | * | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-143-23/+30
| | |\ \ \ | | | | | | | | | | | | | | | | | | eddie/abc9_required
| | * \ \ \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-122-3/+2
| | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | eddie/abc9_required
| | * | | | | Add abc9_required to DSP48E1.{A,B,C,D,PCIN}Eddie Hung2020-01-101-38/+117
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| | * | | | | abc9_ops -prep_times: generate flop boxes from abc9_required attrEddie Hung2020-01-101-61/+0
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| | * | | | | Add abc9_ops -check, -prep_times, -write_box for required timesEddie Hung2020-01-101-0/+5
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| | * | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-086-1676/+520
| | |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | eddie/abc9_required
| | * \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-0639-656/+1189
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | xaig_arrival_required
| | | * \ \ \ \ \ Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactorEddie Hung2020-01-0212-756/+722
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| | | * \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-0227-91/+118
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| | | * \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactorEddie Hung2019-12-306-121/+673
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| | * | | | | | | | | | ConsistencyEddie Hung2019-12-271-1/+1
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| | * | | | | | | | | | Update some abc9_arrival times, add abc9_required timesEddie Hung2019-12-273-24/+220
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| * | | | | | | | | | | Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-033-0/+3
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| * | | | | | | | | | | xilinx: use RAM32M/RAM64M for memories with two read portsMarcin Kościelnicki2020-02-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes inefficient LUT RAM usage for memories with one write and two read ports (commonly used as register files).
| * | | | | | | | | | | Merge pull request #1659 from YosysHQ/clifford/experimentalClaire Wolf2020-01-291-1/+1
| |\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | Add log_experimental() and experimental() API and "yosys -x"
| | * | | | | | | | | | | Add log_experimental() and experimental() API and "yosys -x"Claire Wolf2020-01-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <clifford@clifford.at>
| * | | | | | | | | | | | synth_xilinx: cleanup helpEddie Hung2020-01-281-6/+4
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| * | | | | | | | | | | | synth_xilinx: fix help when no active_design; fixes #1664Eddie Hung2020-01-281-2/+3
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| * | | | | | | | | | | | xilinx: Add simulation model for DSP48 (Virtex 4).Marcin Kościelnicki2020-01-296-45/+534
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| * | | | | | | | | | | | Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_lutsEddie Hung2020-01-284-148/+100
| |\ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unpermute LUT ordering for ice40/ecp5/xilinx
| | * | | | | | | | | | | | Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwardsEddie Hung2020-01-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just like Verilog...
| | * | | | | | | | | | | | Import tests from #1628Eddie Hung2020-01-271-2/+2
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| | * | | | | | | | | | | | xilinx/ice40/ecp5: undo permuting LUT masks in lut_mapEddie Hung2020-01-273-146/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now done in read_aiger
| * | | | | | | | | | | | | Fix unresolved conflict from #1573Eddie Hung2020-01-281-1/+1
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| * | | | | | | | | | | | | Merge pull request #1573 from YosysHQ/eddie/xilinx_tristateN. Engelhardt2020-01-281-0/+3
| |\ \ \ \ \ \ \ \ \ \ \ \ \ | | |/ / / / / / / / / / / / | |/| | | | | | | | | | | | synth_xilinx: error out if tristate without '-iopad'
| | * | | | | | | | | | | | Duplicate tribuf call, credit to @mwkmwkmwkEddie Hung2019-12-131-1/+0
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| | * | | | | | | | | | | | synth_xilinx: error out if tristate without '-iopad'Eddie Hung2019-12-121-0/+4
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| * | | | | | | | | | | | | Merge pull request #1619 from YosysHQ/eddie/abc9_refactorEddie Hung2020-01-271-8/+8
| |\ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|_|_|_|_|_|_|_|_|_|/ | | |/| | | | | | | | | | | Refactor `abc9` pass
| | * | | | | | | | | | | | Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0Eddie Hung2020-01-221-1/+1
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| | * | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-214-128/+98
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| | * | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-151-1/+1
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| | * | | | | | | | | | | | Adding (* techmap_autopurge *) to FD* in abc9_map.vEddie Hung2020-01-141-8/+8
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| * | | | | | | | | | | | | Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warningsEddie Hung2020-01-274-6/+10
| |\ \ \ \ \ \ \ \ \ \ \ \ \ | | |_|_|_|_|/ / / / / / / / | |/| | | | | | | | | | | | ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
| | * | | | | | | | | | | | ice40: reduce ABC9 internal fanout warnings with a param for CI->I3Eddie Hung2020-01-244-6/+10
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| * | | | | | | | | | | | ice40: add SB_SPRAM256KA arrival timeEddie Hung2020-01-241-0/+1
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| * | | | | | | | | | | | Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0Eddie Hung2020-01-231-1/+1
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* | | | | | | | | | | | Explicitly create separate $mux cellsEddie Hung2020-01-211-2/+2
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