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Author
Age
Files
Lines
*
Realistic delays for RAM32X1D too
Eddie Hung
2019-06-25
1
-2
/
+2
*
Add RAM32X1D box info
Eddie Hung
2019-06-25
2
-4
/
+12
*
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-06-25
5
-8
/
+72
|
\
|
*
Add RAM32X1D support
Eddie Hung
2019-06-24
5
-20
/
+73
*
|
Use LUT delays for dist RAM delays
Eddie Hung
2019-06-24
1
-4
/
+4
*
|
Re-enable dist RAM boxes for ECP5
Eddie Hung
2019-06-24
1
-1
/
+1
*
|
Revert "Re-enable dist RAM boxes for ECP5"
Eddie Hung
2019-06-24
1
-1
/
+1
*
|
Re-enable dist RAM boxes for ECP5
Eddie Hung
2019-06-24
1
-1
/
+1
*
|
Add Xilinx dist RAM as comb boxes
Eddie Hung
2019-06-24
2
-0
/
+16
*
|
Add comments to ecp5 box
Eddie Hung
2019-06-22
1
-0
/
+6
*
|
Add comment to xc7 box
Eddie Hung
2019-06-22
1
-0
/
+3
*
|
Fix and cleanup ice40 boxes for carry in/out
Eddie Hung
2019-06-22
4
-313
/
+25
*
|
Carry in/out box ordering now move to end, not swap with end
Eddie Hung
2019-06-22
1
-12
/
+12
*
|
Remove DFF and RAMD box info for now
Eddie Hung
2019-06-21
2
-36
/
+0
*
|
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-06-21
1
-4
/
+5
|
\
|
|
*
ecp5: Improve mapping of $alu when BI is used
David Shah
2019-06-21
1
-4
/
+5
*
|
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-06-20
1
-1
/
+1
|
\
|
|
*
Fixed small typo in ice40_unlut help summary
acw1251
2019-06-19
1
-1
/
+1
|
*
Fixed the help summary line for a few commands
acw1251
2019-06-19
1
-1
/
+1
*
|
Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
Eddie Hung
2019-06-20
1
-0
/
+1
*
|
Really permute Xilinx LUT mappings as default LUT6.I5:A6
Eddie Hung
2019-06-18
1
-16
/
+16
*
|
Revert "Fix (do not) permute LUT inputs, but permute mux selects"
Eddie Hung
2019-06-18
1
-33
/
+31
*
|
Clean up
Eddie Hung
2019-06-18
1
-6
/
+4
*
|
Fix (do not) permute LUT inputs, but permute mux selects
Eddie Hung
2019-06-18
1
-31
/
+33
*
|
Fix copy-pasta issue
Eddie Hung
2019-06-17
1
-9
/
+8
*
|
Permute INIT for +/xilinx/lut_map.v
Eddie Hung
2019-06-17
1
-32
/
+58
*
|
Simplify comment
Eddie Hung
2019-06-17
1
-1
/
+1
*
|
Update LUT7/8 delays to take account for [ABC]OUTMUX delay
Eddie Hung
2019-06-17
1
-5
/
+5
*
|
Try -W 300
Eddie Hung
2019-06-17
1
-1
/
+2
*
|
Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O
Eddie Hung
2019-06-15
1
-2
/
+2
*
|
As per @daveshah1 remove async DFF timing from xilinx
Eddie Hung
2019-06-14
1
-2
/
+2
*
|
Resolve comments from @daveshah1
Eddie Hung
2019-06-14
1
-1
/
+1
*
|
Add XC7_WIRE_DELAY macro to synth_xilinx.cc
Eddie Hung
2019-06-14
1
-1
/
+3
*
|
Update delays based on SymbiFlow/prjxray-db
Eddie Hung
2019-06-14
1
-12
/
+13
*
|
Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}
Eddie Hung
2019-06-14
4
-3
/
+3
*
|
Comment out dist RAM boxing on ECP5 for now
Eddie Hung
2019-06-14
1
-1
/
+1
*
|
Remove WIP ABC9 flop support
Eddie Hung
2019-06-14
4
-46
/
+46
*
|
Make doc consistent
Eddie Hung
2019-06-14
3
-3
/
+6
*
|
ecp5: Add abc9 option
David Shah
2019-06-14
6
-70
/
+184
*
|
Fix name clash
Eddie Hung
2019-06-13
1
-4
/
+8
*
|
Fix LP SB_LUT4 timing
Eddie Hung
2019-06-13
1
-1
/
+1
*
|
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
Eddie Hung
2019-06-12
1
-0
/
+8
*
|
Reduce diff with master
Eddie Hung
2019-06-12
1
-1
/
+1
*
|
Remove abc_flop{,_d} attributes from ice40/cells_sim.v
Eddie Hung
2019-06-12
1
-40
/
+20
*
|
Fix spacing
Eddie Hung
2019-06-12
1
-6
/
+6
*
|
Remove wide mux inference
Eddie Hung
2019-06-12
4
-194
/
+3
*
|
Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"
Eddie Hung
2019-06-12
1
-1
/
+1
*
|
Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"
Eddie Hung
2019-06-12
1
-1
/
+1
*
|
Add "-W' wire delay arg to abc9, use from synth_xilinx
Eddie Hung
2019-06-11
1
-1
/
+1
*
|
Disable dist RAM boxes due to comb loop
Eddie Hung
2019-06-11
1
-2
/
+2
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