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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 08:49:15 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 08:49:15 -0700 |
| commit | 1e838a8913afa36a57d425f26ea881f5071b8b5d (patch) | |
| tree | c46b5e6f6f0f94a55f6601193f98b3ca9d83ff50 /techlibs | |
| parent | 4c9fde87d170fc8d4b729581b055407553951e4c (diff) | |
| download | yosys-1e838a8913afa36a57d425f26ea881f5071b8b5d.tar.gz yosys-1e838a8913afa36a57d425f26ea881f5071b8b5d.tar.bz2 yosys-1e838a8913afa36a57d425f26ea881f5071b8b5d.zip | |
Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index f5f8c43e0..f966115cd 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -297,7 +297,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_luts")) { if (abc == "abc9") - run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : "")); + run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box -W 160" + string(retime ? " -dff" : "")); else if (help_mode) run(abc + " -luts 2:2,3,6:5,10,20 [-dff]"); else |