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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 09:34:41 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 09:34:41 -0700 |
| commit | c7f5091c2fac374c4e48cd9736c2727d65acdcf9 (patch) | |
| tree | c9c772ad0d60e71aa4eef1d33c6864d18330bffc /techlibs | |
| parent | f9433cc34bd52d4807c318a6b26f63cdd15d35c0 (diff) | |
| download | yosys-c7f5091c2fac374c4e48cd9736c2727d65acdcf9.tar.gz yosys-c7f5091c2fac374c4e48cd9736c2727d65acdcf9.tar.bz2 yosys-c7f5091c2fac374c4e48cd9736c2727d65acdcf9.zip | |
Reduce diff with master
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 56a3eb6fc..3ac19e498 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -290,7 +290,7 @@ struct SynthXilinxPass : public ScriptPass // has performed any necessary retiming if (!nosrl || help_mode) run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')"); - run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v"); + run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v"); run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); run("clean"); |