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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 23:05:28 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 09:34:28 -0700 |
| commit | 480a04cb3c3b6a2eb097a78f68fa9ff79caad24e (patch) | |
| tree | 5ab528bd619ca6da7c44d7d77a82839787b083ae /techlibs | |
| parent | 609535739036c30efc35a57730e5ffe968267cdb (diff) | |
| download | yosys-480a04cb3c3b6a2eb097a78f68fa9ff79caad24e.tar.gz yosys-480a04cb3c3b6a2eb097a78f68fa9ff79caad24e.tar.bz2 yosys-480a04cb3c3b6a2eb097a78f68fa9ff79caad24e.zip | |
Realistic delays for RAM32X1D too
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/abc_xc7.box | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 1a7243f54..96966a71c 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -34,8 +34,8 @@ CARRY4 3 1 10 8 # Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE # Outputs: DPO SPO RAM32X1D 4 0 13 2 -- - - - - - 124 124 124 124 124 - - -124 124 124 124 124 - - - - - - - - +- - - - - - 631 472 407 238 127 - - +631 472 407 238 127 - - - - - - - - # SLICEM/A6LUT # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE |