iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Cleanup use of hard-coded default parameters in light of #1945	Eddie Hung	2020-04-22	2	-12/+6
*	intel_alm: Documentation improvements	Dan Ravensloft	2020-04-21	3	-14/+127
*	Use default parameter value in getParam	Marcelina Kościelnicka	2020-04-21	1	-3/+3
*	ecp5: Force SIGNED ports to be 1 bit	David Shah	2020-04-16	1	-1/+1
*	Fix the truth table for $_SR_* cells.	Marcelina Kościelnicka	2020-04-15	3	-26/+21
*	Get rid of dffsr2dff.	Marcelina Kościelnicka	2020-04-15	9	-10/+1
*	synth_intel_alm: VQM support	Dan Ravensloft	2020-04-15	2	-6/+3
*	synth_intel_alm: alternative synthesis for Intel FPGAs	Dan Ravensloft	2020-04-15	18	-1/+1453
*	Merge pull request #1603 from whitequark/ice40-ram_style	whitequark	2020-04-10	5	-2/+137
\|\
\| *	ecp5: do not map FFRAM if explicitly requested otherwise.	whitequark	2020-04-03	1	-1/+3
\| *	ice40: do not map FFRAM if explicitly requested otherwise.	whitequark	2020-04-03	1	-1/+3
\| *	ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.	whitequark	2020-02-06	2	-0/+71
\| *	ice40: match memory inference attribute values case insensitive.	whitequark	2020-02-06	1	-0/+1
\| *	ice40: add support for both 1364.1 and LSE RAM/ROM attributes.	whitequark	2020-02-06	1	-0/+59
* \|	Merge pull request #1648 from YosysHQ/eddie/cmp2lcu	Eddie Hung	2020-04-03	5	-13/+121
\|\ \
\| * \|	cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmp	Eddie Hung	2020-04-03	1	-1/+1
\| * \|	cmp2lcu: fail if `LUT_WIDTH < 2	Eddie Hung	2020-04-03	1	-1/+1
\| * \|	synth: only techmap cmp2{lut,lcu} if -lut	Eddie Hung	2020-04-03	1	-1/+1
\| * \|	synth: use +/cmp2lcu.v in generic 'synth' too	Eddie Hung	2020-04-03	1	-2/+2
\| * \|	Cleanup +/cmp2lut.v	Eddie Hung	2020-04-03	1	-8/+0
\| * \|	synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'	Eddie Hung	2020-04-03	1	-2/+1
\| * \|	+/cmp2lcu.v to work efficiently for fully/partially constant inputs	Eddie Hung	2020-04-03	1	-33/+42
\| * \|	Refactor +/cmp2lcu.v into recursive techmap	Eddie Hung	2020-04-03	1	-38/+65
\| * \|	Cleanup	Eddie Hung	2020-04-03	1	-31/+28
\| * \|	Cleanup cmp2lcu.v	Eddie Hung	2020-04-03	1	-16/+16
\| * \|	techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu	Eddie Hung	2020-04-03	2	-0/+84
\| * \|	cmp2lut: comment out unused since 362f4f9	Eddie Hung	2020-04-03	1	-8/+8
* \| \|	Merge pull request #1767 from YosysHQ/eddie/idstrings	Eddie Hung	2020-04-02	16	-387/+387
\|\ \ \
\| * \| \|	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	16	-366/+366
\| * \| \|	kernel: use more ID::*	Eddie Hung	2020-04-02	5	-26/+26
\| \|/ /
* / /	simcells.v: Generate the fine FF cell types by a python script.	Marcin Kościelnicki	2020-04-02	2	-19/+270
\|/ /
* \|	Fix indentation in `techlibs/ice40/synth_ice40.cc`.	Alberto Gonzalez	2020-04-01	1	-4/+4
* \|	Merge pull request #1794 from YosysHQ/dave/mince-abc9-fix	David Shah	2020-03-21	1	-0/+1
\|\ \
\| * \|	ice40: Map unmapped 'mince' DFFs to gate level	David Shah	2020-03-20	1	-0/+1
* \| \|	ice40: Fix typos in SPRAM ABC9 timing specs	Sylvain Munaut	2020-03-20	1	-2/+2
\|/ /
* \|	xilinx: Mark IOBUFDS.IOB as external pad	Marcin Kościelnicki	2020-03-20	2	-1/+2
* \|	ice40: Fix SPRAM model to keep data stable if chipselect is low	Sylvain Munaut	2020-03-14	1	-5/+8
* \|	Fix invalid verilog syntax	Miodrag Milanovic	2020-03-14	1	-1/+1
* \|	Merge pull request #1716 from zeldin/ecp5_fix	N. Engelhardt	2020-03-09	1	-2/+0
\|\ \
\| * \|	remove unused parameters	N. Engelhardt	2020-03-06	1	-3/+0
\| * \|	ecp5: Add missing parameter to \$__ECP5_PDPW16KD	Marcus Comstedt	2020-02-22	1	-0/+1
* \| \|	ice40: fix specify for ICE40_{LP,U}	Eddie Hung	2020-03-05	1	-4/+4
* \| \|	ice40: fix implicit signal in specify, also clamp negative times to 0	Eddie Hung	2020-03-04	1	-22/+22
* \| \|	Merge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1	Eddie Hung	2020-03-04	4	-109/+244
\|\ \ \
\| * \| \|	xilinx: consider DSP48E1.ADREG	Eddie Hung	2020-03-04	4	-5/+8
\| * \| \|	xilinx: cleanup DSP48E1 handling for abc9	Eddie Hung	2020-03-04	3	-86/+125
\| * \| \|	xilinx: improve specify for DSP48E1	Eddie Hung	2020-03-04	1	-32/+116
\| * \| \|	xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v	Eddie Hung	2020-03-04	2	-5/+14
* \| \| \|	Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabc	N. Engelhardt	2020-03-03	2	-6/+39
\|\ \ \ \ \| \|/ / / \|/\| \| \|
\| * \| \|	Add -flowmap to synth and synth_ice40	Dan Ravensloft	2020-02-28	2	-6/+39