diff options
| author | Sylvain Munaut <tnt@246tNt.com> | 2020-03-14 21:01:42 +0100 |
|---|---|---|
| committer | Sylvain Munaut <tnt@246tNt.com> | 2020-03-14 21:01:42 +0100 |
| commit | acd9eeef7c85f1bd72f42d86bb634769556a04c6 (patch) | |
| tree | bc17453fc9765b02c53dbc4a2fcc8aef55fafb7a /techlibs | |
| parent | acb341745d436987ad764c9198ff0c6ab63c572c (diff) | |
| download | yosys-acd9eeef7c85f1bd72f42d86bb634769556a04c6.tar.gz yosys-acd9eeef7c85f1bd72f42d86bb634769556a04c6.tar.bz2 yosys-acd9eeef7c85f1bd72f42d86bb634769556a04c6.zip | |
ice40: Fix SPRAM model to keep data stable if chipselect is low
According to the official simulation model, and also cross-checked
on real hardware, the data output of the SPRAM when chipselect is
low is kept stable. It doesn't go undefined.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 17fe2ec99..aa1d7aa86 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -2350,16 +2350,19 @@ module SB_SPRAM256KA ( if (off) begin DATAOUT <= 0; end else - if (CHIPSELECT && !STANDBY && !WREN) begin - DATAOUT <= mem[ADDRESS]; - end else begin - if (CHIPSELECT && !STANDBY && WREN) begin + if (STANDBY) begin + DATAOUT <= 'bx; + end else + if (CHIPSELECT) begin + if (!WREN) begin + DATAOUT <= mem[ADDRESS]; + end else begin if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0]; if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4]; if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8]; if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12]; + DATAOUT <= 'bx; end - DATAOUT <= 'bx; end end `endif |