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| author | Miodrag Milanovic <mmicko@gmail.com> | 2020-03-14 14:33:44 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2020-03-14 14:33:44 +0100 |
| commit | acb341745d436987ad764c9198ff0c6ab63c572c (patch) | |
| tree | cff5f0a545581ffc99ca3b423b5368daeb631925 /techlibs | |
| parent | 569e834df2244f214cda8f34daa87ed417089ca1 (diff) | |
| download | yosys-acb341745d436987ad764c9198ff0c6ab63c572c.tar.gz yosys-acb341745d436987ad764c9198ff0c6ab63c572c.tar.bz2 yosys-acb341745d436987ad764c9198ff0c6ab63c572c.zip | |
Fix invalid verilog syntax
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/gate2lut.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/gate2lut.v b/techlibs/common/gate2lut.v index 99c123f4a..15cea3d8d 100644 --- a/techlibs/common/gate2lut.v +++ b/techlibs/common/gate2lut.v @@ -79,7 +79,7 @@ module _90_lut_mux (A, B, S, Y); // A 1010 1010 // B 1100 1100 // S 1111 0000 - .LUT(8'b_1100_1010) + .LUT(8'b 1100_1010) ) lut ( .A(AA), .Y(Y) |