aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
Commit message (Expand)AuthorAgeFilesLines
...
| * | | | Merge branch 'master' into eddie/fix_retimeEddie Hung2019-04-184-44/+69
| |\ \ \ \ | | | |_|/ | | |/| |
| | * | | Merge pull request #928 from litghost/add_xc7_sim_modelsEddie Hung2019-04-123-41/+60
| | |\ \ \
| | | * | | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-123-52/+14
| | | * | | Fix LUT6_2 definition.Keith Rothman2019-04-091-3/+3
| | | * | | Add additional cells sim models for core 7-series primatives.Keith Rothman2019-04-091-0/+57
| | | | |/ | | | |/|
| | * / | Fixing issues in CycloneV cell simDiego2019-04-111-3/+9
| | |/ /
| * | | synth_* with -retime option now calls abc with -D 1 as wellEddie Hung2019-04-1011-15/+15
* | | | Call shregmap twice -- once for variable, another for fixedEddie Hung2019-04-052-8/+14
* | | | Move dffinit til after abcEddie Hung2019-04-053-2/+2
* | | | Merge branch 'eddie/fix_retime' into xc7srlEddie Hung2019-04-054-11/+12
|\| | |
| * | | Move techamp t:$_DFF_?N? to before abc callEddie Hung2019-04-051-2/+2
| * | | RetryEddie Hung2019-04-051-1/+1
| * | | Resolve @daveshah1 comment, update synth_xilinx helpEddie Hung2019-04-052-7/+9
| * | | synth_xilinx to techmap FFs after abc call, otherwise -retime failsEddie Hung2019-04-051-3/+3
| |/ /
* | | techmap inside map_cells stageEddie Hung2019-04-052-2/+1
* | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-0/+1
|\ \ \ | | |/ | |/|
| * | Missing techmap entry in helpEddie Hung2019-04-041-0/+1
* | | Use soft-logic, not LUT3 instantiationEddie Hung2019-04-041-4/+2
* | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-12/+12
|\| |
| * | synth_xilinx to map_cells before map_lutsEddie Hung2019-04-041-12/+12
| |/
* | Cleanup commentsEddie Hung2019-04-041-5/+4
* | t:$dff* -> t:$dff t:$dffeEddie Hung2019-04-041-2/+2
* | -nosrl meant when -nobramEddie Hung2019-04-031-1/+1
* | Remove duplicate STARTUPE2Eddie Hung2019-04-031-1/+0
* | Disable shregmap in synth_xilinx if -retimeEddie Hung2019-04-031-3/+3
* | synth_xilinx to use shregmap with -minlen 3Eddie Hung2019-03-251-2/+2
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-222-24/+31
|\|
| * xilinx: Add keep attribute where appropriateDavid Shah2019-03-222-25/+31
* | Add '-nosrl' option to synth_xilinxEddie Hung2019-03-211-6/+16
* | Fine tune cells_map.vEddie Hung2019-03-201-19/+15
* | Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable lengthEddie Hung2019-03-191-53/+20
* | Add support for variable length Xilinx SRL > 128Eddie Hung2019-03-191-11/+67
* | Restore original synth_xilinx commandsEddie Hung2019-03-191-1/+2
* | Fix spacingEddie Hung2019-03-191-1/+1
* | Fix INIT for variable length SRs that have been bumped up oneEddie Hung2019-03-191-1/+1
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-191-2/+4
|\|
| * Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873Clifford Wolf2019-03-191-2/+4
* | Only accept <128 for variable length, only if $shiftx exclusiveEddie Hung2019-03-161-5/+1
* | Cleanup synth_xilinxEddie Hung2019-03-152-3/+2
* | WorkingEddie Hung2019-03-152-47/+78
* | Reverse bits in INIT parameter for Xilinx, since MSB is shifted firstEddie Hung2019-03-141-16/+32
* | MisspellEddie Hung2019-03-141-1/+1
* | Revert "Add shregmap -init_msb_first and use in synth_xilinx"Eddie Hung2019-03-141-3/+2
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-1433-402/+1656
|\|
| * Remove ice40/cells_sim.v hack to avoid warning for blocking memory writesClifford Wolf2019-03-121-19/+0
| * Fix typo in ice40_braminit help msgClifford Wolf2019-03-091-1/+1
| * Merge pull request #859 from smunaut/ice40_braminitClifford Wolf2019-03-094-37/+212
| |\
| | * ice40: Run ice40_braminit pass by defaultSylvain Munaut2019-03-081-0/+1
| | * ice40: Add ice40_braminit pass to allow initialization of BRAM from fileSylvain Munaut2019-03-083-37/+211
| * | Add link to SF2 / igloo2 macro library guideClifford Wolf2019-03-071-21/+24
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-26 19:39:51 +0000