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Merge branch 'master' into eddie/fix_retime
Eddie Hung
2019-04-18
4
-44
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+69
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Merge pull request #928 from litghost/add_xc7_sim_models
Eddie Hung
2019-04-12
3
-41
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+60
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Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
Keith Rothman
2019-04-12
3
-52
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+14
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Fix LUT6_2 definition.
Keith Rothman
2019-04-09
1
-3
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+3
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Add additional cells sim models for core 7-series primatives.
Keith Rothman
2019-04-09
1
-0
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+57
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Fixing issues in CycloneV cell sim
Diego
2019-04-11
1
-3
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+9
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synth_* with -retime option now calls abc with -D 1 as well
Eddie Hung
2019-04-10
11
-15
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+15
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Call shregmap twice -- once for variable, another for fixed
Eddie Hung
2019-04-05
2
-8
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+14
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Move dffinit til after abc
Eddie Hung
2019-04-05
3
-2
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+2
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Merge branch 'eddie/fix_retime' into xc7srl
Eddie Hung
2019-04-05
4
-11
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+12
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Move techamp t:$_DFF_?N? to before abc call
Eddie Hung
2019-04-05
1
-2
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+2
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Retry
Eddie Hung
2019-04-05
1
-1
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+1
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Resolve @daveshah1 comment, update synth_xilinx help
Eddie Hung
2019-04-05
2
-7
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+9
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synth_xilinx to techmap FFs after abc call, otherwise -retime fails
Eddie Hung
2019-04-05
1
-3
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+3
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techmap inside map_cells stage
Eddie Hung
2019-04-05
2
-2
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+1
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Merge branch 'map_cells_before_map_luts' into xc7srl
Eddie Hung
2019-04-04
1
-0
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+1
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Missing techmap entry in help
Eddie Hung
2019-04-04
1
-0
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+1
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Use soft-logic, not LUT3 instantiation
Eddie Hung
2019-04-04
1
-4
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+2
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Merge branch 'map_cells_before_map_luts' into xc7srl
Eddie Hung
2019-04-04
1
-12
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+12
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synth_xilinx to map_cells before map_luts
Eddie Hung
2019-04-04
1
-12
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+12
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Cleanup comments
Eddie Hung
2019-04-04
1
-5
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+4
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t:$dff* -> t:$dff t:$dffe
Eddie Hung
2019-04-04
1
-2
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+2
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-nosrl meant when -nobram
Eddie Hung
2019-04-03
1
-1
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+1
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Remove duplicate STARTUPE2
Eddie Hung
2019-04-03
1
-1
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+0
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Disable shregmap in synth_xilinx if -retime
Eddie Hung
2019-04-03
1
-3
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+3
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synth_xilinx to use shregmap with -minlen 3
Eddie Hung
2019-03-25
1
-2
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+2
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Merge remote-tracking branch 'origin/master' into xc7srl
Eddie Hung
2019-03-22
2
-24
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+31
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xilinx: Add keep attribute where appropriate
David Shah
2019-03-22
2
-25
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+31
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Add '-nosrl' option to synth_xilinx
Eddie Hung
2019-03-21
1
-6
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+16
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Fine tune cells_map.v
Eddie Hung
2019-03-20
1
-19
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+15
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Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length
Eddie Hung
2019-03-19
1
-53
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+20
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Add support for variable length Xilinx SRL > 128
Eddie Hung
2019-03-19
1
-11
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+67
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Restore original synth_xilinx commands
Eddie Hung
2019-03-19
1
-1
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+2
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Fix spacing
Eddie Hung
2019-03-19
1
-1
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+1
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Fix INIT for variable length SRs that have been bumped up one
Eddie Hung
2019-03-19
1
-1
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+1
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Merge remote-tracking branch 'origin/master' into xc7srl
Eddie Hung
2019-03-19
1
-2
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+4
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Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
Clifford Wolf
2019-03-19
1
-2
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+4
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Only accept <128 for variable length, only if $shiftx exclusive
Eddie Hung
2019-03-16
1
-5
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+1
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Cleanup synth_xilinx
Eddie Hung
2019-03-15
2
-3
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+2
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Working
Eddie Hung
2019-03-15
2
-47
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+78
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Reverse bits in INIT parameter for Xilinx, since MSB is shifted first
Eddie Hung
2019-03-14
1
-16
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+32
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Misspell
Eddie Hung
2019-03-14
1
-1
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+1
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Revert "Add shregmap -init_msb_first and use in synth_xilinx"
Eddie Hung
2019-03-14
1
-3
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+2
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Merge remote-tracking branch 'origin/master' into xc7srl
Eddie Hung
2019-03-14
33
-402
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+1656
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Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes
Clifford Wolf
2019-03-12
1
-19
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+0
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Fix typo in ice40_braminit help msg
Clifford Wolf
2019-03-09
1
-1
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+1
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Merge pull request #859 from smunaut/ice40_braminit
Clifford Wolf
2019-03-09
4
-37
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+212
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ice40: Run ice40_braminit pass by default
Sylvain Munaut
2019-03-08
1
-0
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+1
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ice40: Add ice40_braminit pass to allow initialization of BRAM from file
Sylvain Munaut
2019-03-08
3
-37
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+211
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Add link to SF2 / igloo2 macro library guide
Clifford Wolf
2019-03-07
1
-21
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+24
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