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* Extract ice40_unlut pass from ice40_opt.whitequark2018-12-053-13/+109
* ice40: Add option to only use CE if it'd be use by more than X FFsSylvain Munaut2018-11-271-0/+14
* Merge pull request #697 from eddiehung/xilinx_ps7Clifford Wolf2018-11-122-0/+624
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| * Add support for Xilinx PS7 blockEddie Hung2018-11-102-0/+624
* | Merge pull request #695 from daveshah1/ecp5_bbClifford Wolf2018-11-122-1/+420
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| * ecp5: Add 'fake' DCU parametersDavid Shah2018-11-091-0/+11
| * ecp5: Add blackboxes for ancillary DCU cellsDavid Shah2018-11-091-0/+18
| * ecp5: Adding some blackbox cellsDavid Shah2018-11-072-1/+391
* | Fix sf2 LUT interfaceClifford Wolf2018-10-312-12/+12
* | Basic SmartFusion2 and IGLOO2 synthesis supportClifford Wolf2018-10-315-0/+377
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* ecp5: Remove DSP parameters that don't workDavid Shah2018-10-221-21/+0
* ecp5: Add DSP blackboxesDavid Shah2018-10-213-1/+118
* ecp5: Sim model fixesDavid Shah2018-10-191-3/+5
* ecp5: Add latch inferenceDavid Shah2018-10-193-3/+12
* Merge pull request #657 from mithro/xilinx-vprClifford Wolf2018-10-181-3/+2
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| * xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.Tim 'mithro' Ansell2018-10-081-3/+2
* | ecp5: Disable LSR inversionDavid Shah2018-10-162-21/+21
* | BRAM improvementsDavid Shah2018-10-121-11/+16
* | ecp5: Adding BRAM maps for all size optionsDavid Shah2018-10-101-1/+64
* | ecp5: First BRAM type maps successfullyDavid Shah2018-10-108-10/+76
* | ecp5: Script for BRAM IO connectionsDavid Shah2018-10-104-64/+115
* | ecp5: Adding BRAM initialisation and configDavid Shah2018-10-095-0/+73
* | ecp5: Add blackbox for DP16KDDavid Shah2018-10-051-0/+93
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* Add inout ports to cells_xtra.vClifford Wolf2018-10-042-2/+14
* xilinx: Adding missing inout IO port to IOBUFTim Ansell2018-10-031-0/+1
* Merge pull request #645 from daveshah1/ecp5_dram_fixClifford Wolf2018-10-021-0/+1
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| * ecp5: Don't map ROMs to DRAMDavid Shah2018-10-011-0/+1
* | Add iCE40 SB_SPRAM256KA simulation modelClifford Wolf2018-09-101-9/+30
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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-2016-54/+54
* ecp5: Fixing miscellaneous sim model issuesDavid Shah2018-07-161-2/+2
* ecp5: Fixing 'X' issues with LUT simulation modelsDavid Shah2018-07-161-6/+19
* ecp5: ECP5 synthesis fixesDavid Shah2018-07-163-15/+32
* ecp5: Adding synchronous set/reset supportDavid Shah2018-07-142-21/+42
* ecp5: Add DRAM match ruleDavid Shah2018-07-131-0/+4
* ecp5: Cells and mappings fixesDavid Shah2018-07-132-5/+5
* ecp5: Fixing arith_mapDavid Shah2018-07-131-4/+5
* ecp5: Initial arith_map implementationDavid Shah2018-07-133-6/+80
* ecp5: Adding basic synth_ecp5 based on synth_ice40David Shah2018-07-133-7/+345
* ecp5: Adding DFF mapsDavid Shah2018-07-132-1/+30
* ecp5: Adding DRAM mapDavid Shah2018-07-133-1/+76
* ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7David Shah2018-07-132-0/+473
* ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LCDavid Shah2018-07-131-2/+6
* Add "synth_ice40 -json"Clifford Wolf2018-06-131-9/+22
* Fix ice40_opt for cases where a port is connected to a signal with width != 1Clifford Wolf2018-06-111-9/+25
* Make -nordff the default in "prep"Clifford Wolf2018-05-301-9/+13
* Avoid mixing module port declaration styles in ice40 cells_sim.vOlof Kindgren2018-05-171-43/+23
* Merge pull request #537 from mithro/yosys-vprClifford Wolf2018-05-044-11/+48
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| * Improving vpr output support.Tim 'mithro' Ansell2018-04-184-7/+40
| * synth_ice40: Rework the vpr blif output slightly.Tim 'mithro' Ansell2018-04-181-4/+8
* | Add "synth_intel --noiopads"Clifford Wolf2018-04-301-2/+11
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