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| author | Tim Ansell <me@mith.ro> | 2018-10-03 16:38:32 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-03 16:38:32 -0700 |
| commit | ad975fb694f32edd51b4cf05f62485798e31ef1e (patch) | |
| tree | c2b6a4caf14948c8a45d1bf5117e7c4a8c84ec00 /techlibs | |
| parent | 76baae4b946cdeb04026120b495c87a6146358d0 (diff) | |
| download | yosys-ad975fb694f32edd51b4cf05f62485798e31ef1e.tar.gz yosys-ad975fb694f32edd51b4cf05f62485798e31ef1e.tar.bz2 yosys-ad975fb694f32edd51b4cf05f62485798e31ef1e.zip | |
xilinx: Adding missing inout IO port to IOBUF
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.v | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index a2dd01ad5..f5abf3ae0 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -2225,6 +2225,7 @@ module IOBUF (...); parameter IOSTANDARD = "DEFAULT"; parameter SLEW = "SLOW"; output O; + inout IO; input I, T; endmodule |