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| author | Clifford Wolf <clifford@clifford.at> | 2018-10-18 10:54:03 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-18 10:54:03 +0200 |
| commit | 24a5c6585678f89058382fe2c3f36b821b419e90 (patch) | |
| tree | 7f70862de9da5237bcd987ba30da24c0a8579c7e /techlibs | |
| parent | 93d99559ef940193a77d132fc52449259484aa1a (diff) | |
| parent | b111ea12286b45e51fc453e3f4d7ac906e1a9f7c (diff) | |
| download | yosys-24a5c6585678f89058382fe2c3f36b821b419e90.tar.gz yosys-24a5c6585678f89058382fe2c3f36b821b419e90.tar.bz2 yosys-24a5c6585678f89058382fe2c3f36b821b419e90.zip | |
Merge pull request #657 from mithro/xilinx-vpr
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives when using `-vpr`
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 590fe61d2..b27c08529 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -235,10 +235,9 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_cells")) { + Pass::call(design, "techmap -map +/xilinx/cells_map.v"); if (vpr) - Pass::call(design, "techmap -D NO_LUT -map +/xilinx/cells_map.v"); - else - Pass::call(design, "techmap -map +/xilinx/cells_map.v"); + Pass::call(design, "techmap -map +/xilinx/lut2lut.v"); Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT"); Pass::call(design, "clean"); } |