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* Move xilinx_dsp to before alumaccEddie Hung2019-08-081-6/+4
* INMODE is 5 bitsEddie Hung2019-08-081-1/+1
* Fix copy-pasta typoEddie Hung2019-08-081-2/+2
* ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinxDavid Shah2019-08-081-11/+11
* ecp5: Bring up to date with mul2dsp changesDavid Shah2019-08-082-2/+10
* Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspDavid Shah2019-08-087-125/+278
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| * Run "opt_expr -fine" instead of "wreduce" due to #1213Eddie Hung2019-08-071-2/+1
| * Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-076-123/+277
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| | * Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixesDavid Shah2019-08-071-101/+244
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| | | * ecp5: Make cells_sim.v consistent with nextpnrDavid Shah2019-08-071-101/+244
| | * | Merge pull request #1249 from mmicko/anlogic_fixClifford Wolf2019-08-071-16/+8
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| | | * anlogic : Fix alu mappingMiodrag Milanovic2019-08-031-16/+8
| | * | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+19
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| | * Merge pull request #1239 from mmicko/mingw_fixClifford Wolf2019-08-023-6/+6
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| | | * Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-013-6/+6
* | | | DSP48E1 sim model: add SIMD testsDavid Shah2019-08-083-3/+113
* | | | DSP48E1 model: test CE inputsDavid Shah2019-08-082-7/+17
* | | | DSP48E1 sim model: fix seq tests and add preadder testsDavid Shah2019-08-082-6/+91
* | | | DSP48E1 sim model: seq test workingDavid Shah2019-08-083-16/+60
* | | | DSP48E1 sim model: Comb, no pre-adder, mode workingDavid Shah2019-08-082-8/+13
* | | | [wip] sim model testingDavid Shah2019-08-084-15/+77
* | | | [wip] sim model testingDavid Shah2019-08-083-40/+360
* | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-071-6/+82
* | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-23/+120
* | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-8/+75
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* | | Trim Y_WIDTHEddie Hung2019-08-011-5/+3
* | | Add DSP_SIGNEDONLY backEddie Hung2019-08-011-0/+16
* | | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTHEddie Hung2019-08-012-5/+12
* | | Change $__softmul back to $mulEddie Hung2019-08-011-0/+1
* | | Revert "Do not do sign extension in techmap; let packer do it"Eddie Hung2019-08-011-5/+14
* | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-016-18/+24
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| * | RST -> RSTBRST for RAMB8BWEREddie Hung2019-07-291-3/+3
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| * Merge branch 'ZirconiumX-synth_intel_m9k'Clifford Wolf2019-07-254-5/+11
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| | * intel: Map M9K BRAM only on families that have itDan Ravensloft2019-07-234-5/+12
| * | Merge pull request #1218 from ZirconiumX/synth_intel_iopadsClifford Wolf2019-07-251-8/+8
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| | * | intel: Make -noiopads the defaultDan Ravensloft2019-07-241-8/+8
| * | | Merge pull request #1224 from YosysHQ/xilinx_fix_ffEddie Hung2019-07-251-2/+2
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| | * | xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
* | | | Fix B_WIDTH > DSP_B_MAXWIDTH caseEddie Hung2019-08-011-32/+14
* | | | Do not compute sign bit if result is zeroEddie Hung2019-07-311-1/+2
* | | | For signed multipliers, compute sign bit separately...Eddie Hung2019-07-311-23/+42
* | | | Fix spacingEddie Hung2019-07-261-3/+3
* | | | Add copyright header, comment on cascadeEddie Hung2019-07-241-4/+34
* | | | Typo for Y_WIDTHEddie Hung2019-07-231-1/+1
* | | | Remove debugEddie Hung2019-07-221-1/+0
* | | | Rename according to vendor doc TN1295Eddie Hung2019-07-221-0/+1
* | | | opt and wreduce necessary for -dspEddie Hung2019-07-221-2/+4
* | | | Use minimum sized width wiresEddie Hung2019-07-221-7/+13
* | | | Indirection via $__soft_mulEddie Hung2019-07-192-9/+10
* | | | Do not do sign extension in techmap; let packer do itEddie Hung2019-07-191-14/+5
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