aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
Commit message (Expand)AuthorAgeFilesLines
...
| | * | | | fix BRAM width and initPepijn de Vos2019-09-062-12/+28
| | * | | | add more DFF to sim libPepijn de Vos2019-09-062-6/+111
| | * | | | WIP aditional DFF primitivesPepijn de Vos2019-09-052-1/+48
| | * | | | support bram initialisationPepijn de Vos2019-09-055-3/+25
| | * | | | use singleton ground and vcc nets, apparently this makes pnr happierPepijn de Vos2019-09-051-1/+1
| | * | | | add MUX supportPepijn de Vos2019-09-053-0/+17
| | * | | | set undriven pads to zeroPepijn de Vos2019-09-041-0/+1
| | * | | | Merge remote-tracking branch 'diego/gowin'Pepijn de Vos2019-09-042-2/+2
| | |\ \ \ \
| | | * | | | Updating gowinDiego H2019-09-022-2/+2
| | * | | | | gowin: add splitnets to appease the PnRPepijn de Vos2019-09-041-0/+1
| * | | | | | xilinx: Add simulation models for MULT18X18* and DSP48A*.Marcin Kościelnicki2019-11-193-132/+516
| | |_|_|_|/ | |/| | | |
| * | | | | ecp5: Use new autoname pass for better cell/net namesDavid Shah2019-11-151-0/+1
| * | | | | Merge pull request #1490 from YosysHQ/clifford/autonameClifford Wolf2019-11-141-0/+1
| |\ \ \ \ \
| | * | | | | Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-131-0/+1
| * | | | | | Merge pull request #1465 from YosysHQ/dave/ice40_timing_simClifford Wolf2019-11-141-14/+436
| |\ \ \ \ \ \ | | |/ / / / / | |/| | | | |
| | * | | | | ice40: Add post-pnr ICESTORM_RAM model and fix FFsDavid Shah2019-10-231-2/+340
| | * | | | | ice40: Support for post-pnr timing simulationDavid Shah2019-10-231-12/+96
| * | | | | | Do not map $eq and $ne in cmp2lut, only proper arithmetic cmpClifford Wolf2019-11-111-1/+1
| | |_|_|_|/ | |/| | | |
| * | | | | synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-0611-23234/+29820
| * | | | | xilinx: Add URAM288 mapping for xcupDavid Shah2019-10-235-2/+92
| * | | | | xilinx: Add support for UltraScale[+] BRAM mappingDavid Shah2019-10-237-416/+1062
| * | | | | xilinx: Support multiplier mapping for all families.Marcin Kościelnicki2019-10-229-9/+269
| * | | | | Merge pull request #1452 from nakengelhardt/fix_dsp_mem_regClifford Wolf2019-10-222-0/+2
| |\ \ \ \ \ | | |_|_|_|/ | |/| | | |
| | * | | | Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-172-0/+2
| * | | | | ecp5: Pass -nomfs to abc9David Shah2019-10-201-2/+2
| | |/ / / | |/| | |
| * | | | Makefile: don't assume python is called `python3`Sean Cross2019-10-194-6/+6
| * | | | Merge branch 'master' into mmicko/efinixMiodrag Milanović2019-10-1837-474/+305
| |\| | |
| | * | | ecp5: Add ECLKBRIDGECS blackboxDavid Shah2019-10-111-0/+7
| | * | | ecp5: Add attrmvcp to copy syn_useioff to driving FFDavid Shah2019-10-101-0/+1
| | * | | ecp5: Set syn_useioff on IO FFs to enable packingDavid Shah2019-10-101-8/+8
| | * | | xilinx: Add simulation model for IBUFG.Marcin Kościelnicki2019-10-105-33/+14
| * | | | FF should be initialized to 0Miodrag Milanovic2019-10-041-1/+3
| * | | | Add missing latch mappingMiodrag Milanovic2019-10-041-0/+12
* | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-081-5/+9
|\ \ \ \ \ | | |/ / / | |/| | |
| * | | | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9Eddie Hung2019-10-0831-228/+236
| |\ \ \ \
| | * \ \ \ Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-044-181/+9
| | |\ \ \ \
| * | | | | | Add comment on why partial multipliers are 18x18Eddie Hung2019-10-041-4/+8
| * | | | | | Fix typo in check_label()Eddie Hung2019-10-041-1/+1
| | |/ / / / | |/| | | |
* | | | | | CleanupEddie Hung2019-10-071-7/+2
* | | | | | Rename $currQ to $abc9_currQEddie Hung2019-10-071-46/+46
* | | | | | Update comments in abc9_map.vEddie Hung2019-10-071-131/+57
* | | | | | Remove -D_ABC9Eddie Hung2019-10-071-2/+0
* | | | | | Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-054-230/+200
* | | | | | abc -> abc9Eddie Hung2019-10-041-3/+3
* | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-044-181/+9
|\| | | | |
| * | | | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-2/+6
| * | | | | Remove DSP48E1 from *_cells_xtra.vEddie Hung2019-10-043-178/+2
* | | | | | Use read_args for read_verilogEddie Hung2019-10-041-3/+6
* | | | | | Fix merge issuesEddie Hung2019-10-042-9/+10
* | | | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-0431-278/+294
|\ \ \ \ \ \ | | |/ / / / | |/| | | |