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author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-09-05 13:36:41 +0200 |
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committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-09-05 13:36:41 +0200 |
commit | 3eff2271d0fe25632f7e6b22cf0be078d2cd9990 (patch) | |
tree | 45ac22fbb2a8564f37ab3c3a48c6809d5a21646f /techlibs | |
parent | ae93c034adc8a7d14a9f39175dacdddda75ea7a2 (diff) | |
download | yosys-3eff2271d0fe25632f7e6b22cf0be078d2cd9990.tar.gz yosys-3eff2271d0fe25632f7e6b22cf0be078d2cd9990.tar.bz2 yosys-3eff2271d0fe25632f7e6b22cf0be078d2cd9990.zip |
add MUX support
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/gowin/cells_map.v | 3 | ||||
-rw-r--r-- | techlibs/gowin/cells_sim.v | 13 | ||||
-rw-r--r-- | techlibs/gowin/synth_gowin.cc | 1 |
3 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v index ebdc88a0a..c38805b91 100644 --- a/techlibs/gowin/cells_map.v +++ b/techlibs/gowin/cells_map.v @@ -5,6 +5,9 @@ module \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), module \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule module \$__DFFS_PP1_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule +module \$_MUX_ (input A, B, S, output Y); MUX2 _TECHMAP_REPLACE_ (.I0(A), .I1(B), .S0(S), .O(Y)); endmodule +module \$_MUX4_ (input A, B, C, D, S, T, output Y); MUX4 _TECHMAP_REPLACE_ (.I0(A), .I1(B), .I2(C), .I3(D), .S0(S), .S1(T), .O(Y)); endmodule + module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index ebb238bad..98dfef9bf 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -24,6 +24,19 @@ module LUT4(output F, input I0, I1, I2, I3); assign F = I0 ? s1[1] : s1[0]; endmodule +module MUX2 (I0, I1, S0, O); +input I0, I1, S0; +output O; +assign O = S0 ? I1 : I0; +endmodule + +module MUX4 (I0, I1, I2, I3, S0, S1, O); +input I0, I1, I2, I3, S0, S1; +output O; +assign O = S1 ? (S0 ? I3 : I2) : + (S0 ? I1 : I0); +endmodule + module DFF (output reg Q, input CLK, D); parameter [0:0] INIT = 1'b0; initial Q = INIT; diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index f7a5006bc..4d32f62d4 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -196,6 +196,7 @@ struct SynthGowinPass : public ScriptPass run("opt_clean"); if (!nodffe) run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*"); + run("muxcover -mux4"); run("techmap -map +/gowin/cells_map.v"); run("opt_expr -mux_undef"); run("simplemap"); |