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* Add no MULT no DPORT configEddie Hung2019-09-134-226/+471
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* Add support for MULT and DPORTEddie Hung2019-09-134-10/+588
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* Refine diagramEddie Hung2019-09-131-12/+14
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* Add an ASCII drawingEddie Hung2019-09-121-3/+22
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* Finish explanationEddie Hung2019-09-122-5/+20
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* Rename to techmap_guardEddie Hung2019-09-121-2/+3
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* Initial DSP48E1 box supportEddie Hung2019-09-124-0/+867
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* Set more ports explicitlyEddie Hung2019-09-121-1/+2
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* Missing spaceEddie Hung2019-09-111-0/+1
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* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-115-53/+219
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| * synth_xilinx: Support init values on Spartan 6 flip-flops properly.Marcin Koƛcielnicki2019-09-075-53/+219
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* | Move "(skip if -nodsp)" message to labelEddie Hung2019-09-101-4/+4
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* | Really get rid of 'opt_expr -fine' by being explicitEddie Hung2019-09-101-3/+0
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* | Remove wreduce callEddie Hung2019-09-101-1/+0
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* | Add comment for why opt_expr is necessaryEddie Hung2019-09-101-0/+2
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* | Revert "Remove "opt_expr -fine" call"Eddie Hung2019-09-101-0/+1
| | | | | | | | This reverts commit bfda921d0317bfb4cb6fc9de8a556c2258b709bc.
* | Rename label to map_dspEddie Hung2019-09-101-1/+1
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* | Remove "opt_expr -fine" callEddie Hung2019-09-101-1/+0
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* | Set USE_MULT and USE_SIMDEddie Hung2019-09-091-1/+3
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* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-059-55/+301
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| * Resolve TODO with pin assignments for SRL*Eddie Hung2019-09-041-4/+2
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| * Add commentsEddie Hung2019-09-021-1/+9
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| * Remove trailing spaceEddie Hung2019-08-301-2/+2
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| * Merge branch 'eddie/xilinx_srl' into xaig_arrivalEddie Hung2019-08-281-15/+22
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| * \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-287-195/+653
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| * | | Put attributes above portEddie Hung2019-08-232-27/+62
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| * | | Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-231-5/+10
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| * | | | Use semicolonEddie Hung2019-08-211-1/+1
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| * | | | techmap before readEddie Hung2019-08-211-1/+1
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| * | | | Add abc_arrival to SRL*Eddie Hung2019-08-211-3/+5
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| * | | | OopsEddie Hung2019-08-201-1/+1
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| * | | | xilinx to use abc_map.v with -max_iter 1Eddie Hung2019-08-206-171/+26
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| * | | | Add reference to FD* timingEddie Hung2019-08-201-0/+2
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| * | | | Remove sequential extensionEddie Hung2019-08-206-359/+17
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| * | | | Remove SRL* delays from cells_sim.vEddie Hung2019-08-201-5/+3
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| * | | | LUTMUX -> LUTMUX6Eddie Hung2019-08-201-2/+2
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| * | | | Cleanup techmap in map_lutsEddie Hung2019-08-201-3/+5
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| * | | | Move `techmap abc_map.v` into map_lutsEddie Hung2019-08-201-1/+2
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| * | | | Remove delays from abc_map.vEddie Hung2019-08-201-5/+2
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| * | | | TypoEddie Hung2019-08-201-1/+1
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-204-16/+19
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| * | | | | Wrap SRL{16,32} tooEddie Hung2019-08-203-7/+98
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| * | | | | Wrap LUTRAMs in order to capture comb/seq behaviourEddie Hung2019-08-205-36/+200
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| * | | | | Add LUTRAM delaysEddie Hung2019-08-201-3/+6
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| * | | | | Remove mapping rulesEddie Hung2019-08-201-33/+0
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| * | | | | Remove -icellsEddie Hung2019-08-201-2/+2
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| * | | | | Use abc_{map,unmap,model}.vEddie Hung2019-08-207-110/+324
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-201-2/+2
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| * | | | | | Add arrival times for SRL outputsEddie Hung2019-08-191-3/+5
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| * | | | | | Add BRAM arrival timesEddie Hung2019-08-191-8/+10
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