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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-09 20:56:29 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-09 20:56:29 -0700 |
| commit | a7e60322878913886278d537365baf939182a1d9 (patch) | |
| tree | 627fcb6403ac9ecf934e2ad242846fcdd46055f3 /techlibs/xilinx | |
| parent | 6348f9512c5dd9de9529a5e6cac58ad46a742309 (diff) | |
| download | yosys-a7e60322878913886278d537365baf939182a1d9.tar.gz yosys-a7e60322878913886278d537365baf939182a1d9.tar.bz2 yosys-a7e60322878913886278d537365baf939182a1d9.zip | |
Set USE_MULT and USE_SIMD
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/dsp_map.v | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index fdd55afe3..cc37f0085 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -23,7 +23,9 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); .INMODEREG(0), .MREG(0), .OPMODEREG(0), - .PREG(0) + .PREG(0), + .USE_MULT("MULTIPLY"), + .USE_SIMD("ONE48") ) _TECHMAP_REPLACE_ ( //Data path .A({{5{A[24]}}, A}), |