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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 17:55:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 17:55:12 -0700 |
| commit | 3b52d6e29ccc95fd4d102d9a59bb34125521c648 (patch) | |
| tree | 53cae04de53abb8e91f9f2a8eabde510cf1c9407 /techlibs/xilinx | |
| parent | 54284aaa986800b8623d401fd93cf92d25d13713 (diff) | |
| download | yosys-3b52d6e29ccc95fd4d102d9a59bb34125521c648.tar.gz yosys-3b52d6e29ccc95fd4d102d9a59bb34125521c648.tar.bz2 yosys-3b52d6e29ccc95fd4d102d9a59bb34125521c648.zip | |
Move `techmap abc_map.v` into map_luts
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index d6ff91e13..a2ec6a9c9 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -380,7 +380,7 @@ struct SynthXilinxPass : public ScriptPass if (widemux > 0) techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux); if (abc9) - techmap_args += " -map +/xilinx/ff_map.v -map +/xilinx/abc_map.v"; + techmap_args += " -map +/xilinx/ff_map.v"; run("techmap " + techmap_args); run("clean"); } @@ -393,6 +393,7 @@ struct SynthXilinxPass : public ScriptPass if (family != "xc7") log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n"); run("read_verilog -icells -lib +/xilinx/abc_model.v"); + run("techmap -map +/xilinx/abc_map.v"; if (nowidelut) run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); else |