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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 12:00:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 12:00:12 -0700 |
| commit | c4d4c6db3f4bff22b2fa3a152c5c33d648af81f8 (patch) | |
| tree | b465265f1bc72f0b943fc6e4be7f4661e4e5734d /techlibs/xilinx | |
| parent | 1f03154a0cc08c1bde59036d6b0a4a40a3898c3d (diff) | |
| parent | 14c03861b6d178c85d6963e673ed51bc142457e1 (diff) | |
| download | yosys-c4d4c6db3f4bff22b2fa3a152c5c33d648af81f8.tar.gz yosys-c4d4c6db3f4bff22b2fa3a152c5c33d648af81f8.tar.bz2 yosys-c4d4c6db3f4bff22b2fa3a152c5c33d648af81f8.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index e5d9f480b..dd5a76752 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -183,9 +183,9 @@ endmodule (* abc_box_id = 4, lib_whitebox *) module CARRY4( - (* abc_carry_out *) output [3:0] CO, + (* abc_carry *) output [3:0] CO, output [3:0] O, - (* abc_carry_in *) input CI, + (* abc_carry *) input CI, input CYINIT, input [3:0] DI, S ); |