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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 11:27:42 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 11:27:42 -0700 |
| commit | 584c68069194f7c776755c108801a56898e19fff (patch) | |
| tree | 434cfd3963190905579a7a17911476637e79d9af /techlibs/xilinx | |
| parent | 8182cb9d91555d5be52abbfeeb5d22af05342d8a (diff) | |
| download | yosys-584c68069194f7c776755c108801a56898e19fff.tar.gz yosys-584c68069194f7c776755c108801a56898e19fff.tar.bz2 yosys-584c68069194f7c776755c108801a56898e19fff.zip | |
Add abc_arrival to SRL*
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 80211619b..65c59759a 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -355,7 +355,8 @@ module RAM128X1D ( endmodule module SRL16E ( - output Q, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 + (* abc_arrival=1472 *) output Q, input A0, A1, A2, A3, CE, CLK, D ); parameter [15:0] INIT = 16'h0000; @@ -373,8 +374,9 @@ module SRL16E ( endmodule module SRLC32E ( - output Q, - output Q31, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 + (* abc_arrival=1472 *) output Q, + (* abc_arrival=1114 *) output Q31, input [4:0] A, input CE, CLK, D ); |