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* Add BRAM arrival timesEddie Hung2019-08-191-8/+10
* Add reference to source of Tclktoq timingEddie Hung2019-08-191-0/+2
* Add 'abc_arrival' attribute for flop outputsEddie Hung2019-08-191-6/+6
* Update box timingsEddie Hung2019-08-191-6/+9
* Move from cell attr to module attrEddie Hung2019-08-191-12/+6
* Use attributes instead of paramsEddie Hung2019-08-191-30/+12
* Merge branch 'eddie/abc9_refactor' into xaig_dffEddie Hung2019-08-1612-25/+627
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| * Attach abc_scc_break, abc_carry_{in,out} attr to ports not modulesEddie Hung2019-08-161-8/+20
| * stoi -> atoiEddie Hung2019-08-071-1/+1
| * RST -> RSTBRST for RAMB8BWEREddie Hung2019-07-291-3/+3
| * xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
| * Merge pull request #1182 from koriakin/xc6s-bramEddie Hung2019-07-119-8/+598
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| | * synth_xilinx: Initial Spartan 6 block RAM inference support.Marcin Kościelnicki2019-07-119-8/+598
| * | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Viv...Marcin Kościelnicki2019-07-112-6/+6
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* | Add Tsu offset to boxes, and commentsEddie Hung2019-07-111-6/+11
* | ABC doesn't like negative delays in flop boxes...Eddie Hung2019-07-111-6/+6
* | Fix FDCE_1 boxEddie Hung2019-07-111-1/+1
* | Revert "$pastQ should be first input"Eddie Hung2019-07-111-13/+13
* | Propagate INIT attrEddie Hung2019-07-111-5/+5
* | $pastQ should be first inputEddie Hung2019-07-111-13/+13
* | Fix typoEddie Hung2019-07-111-1/+1
* | Simplify to $__ABC_ASYNC boxEddie Hung2019-07-112-19/+8
* | $__ABC_FD_ASYNC_MUX.Q -> YEddie Hung2019-07-111-1/+1
* | Restore from masterEddie Hung2019-07-101-0/+1
* | Another typoEddie Hung2019-07-101-1/+1
* | Fix clk_pol for FD*_1Eddie Hung2019-07-101-3/+3
* | Another typoEddie Hung2019-07-101-1/+1
* | Another typoEddie Hung2019-07-101-1/+1
* | Use \$currQEddie Hung2019-07-101-4/+9
* | Preserve all parameters, plus some extra ones for clk/en polarityEddie Hung2019-07-101-10/+66
* | Change how to specify flops to ABC againEddie Hung2019-07-101-13/+37
* | Remove params from FD*_1 variantsEddie Hung2019-07-101-12/+3
* | Fix typo, and have !{PRE,CLR} behave as CEEddie Hung2019-07-101-14/+14
* | Move ABC FF stuff to abc_ff.v; add support for other FD* typesEddie Hung2019-07-104-27/+135
* | Uncomment IS_C_INVERTED parameterEddie Hung2019-07-101-1/+1
* | synth_xilinx's map_cells stage to techmap ff_map.vEddie Hung2019-07-101-0/+2
* | Fix box numberingEddie Hung2019-07-102-5/+5
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-07-106-75/+446
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| * Merge pull request #1180 from YosysHQ/eddie/no_abc9_retimeEddie Hung2019-07-101-5/+8
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| | * Error out if -abc9 and -retime specifiedEddie Hung2019-07-101-5/+8
| * | Add some spacingEddie Hung2019-07-101-9/+9
| * | Add some ASCII art explaining mux decompositionEddie Hung2019-07-101-0/+21
| * | Call muxpack and pmux2shiftx before cmp2lutEddie Hung2019-07-091-9/+12
| * | Restore opt_clean back to original placeEddie Hung2019-07-091-2/+1
| * | Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6Eddie Hung2019-07-091-0/+2
| * | Extend using A[1] to preserve don't careEddie Hung2019-07-091-1/+9
| * | Extend during mux decomposition with 1'bxEddie Hung2019-07-091-24/+3
| * | Fix typo and commentsEddie Hung2019-07-091-4/+4
| * | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-07-091-19/+25
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| | * Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanupEddie Hung2019-07-021-0/+2
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