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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 17:17:54 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 17:17:54 -0700 |
| commit | 3bb48facb21032eb49ca40150827358e2d35a9c8 (patch) | |
| tree | 1d3fbd245089f7edefeff5b01cc45ab8f9e7cffc /techlibs/xilinx | |
| parent | 0372c900e8dbf6c3d46cdb9438b46d5ddf970e18 (diff) | |
| download | yosys-3bb48facb21032eb49ca40150827358e2d35a9c8.tar.gz yosys-3bb48facb21032eb49ca40150827358e2d35a9c8.tar.bz2 yosys-3bb48facb21032eb49ca40150827358e2d35a9c8.zip | |
Remove params from FD*_1 variants
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/abc_ff.v | 15 |
1 files changed, 3 insertions, 12 deletions
diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v index 015211988..1d9a25ba7 100644 --- a/techlibs/xilinx/abc_ff.v +++ b/techlibs/xilinx/abc_ff.v @@ -98,10 +98,7 @@ endmodule (* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1,D,Q,\\$pastQ" *) module \$__ABC_FDRE_1 (output Q, input C, CE, D, R, \$pastQ ); parameter [0:0] INIT = 1'b0; - //parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_R_INVERTED = 1'b0; - assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ ); + assign Q = R ? 1'b0 : (CE ? D : \$pastQ ); endmodule (* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE,D,Q,\\$pastQ" *) @@ -116,10 +113,7 @@ endmodule (* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1,D,Q,\\$pastQ" *) module \$__ABC_FDCE_1 (output Q, input C, CE, D, CLR, \$pastQ ); parameter [0:0] INIT = 1'b0; - //parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ; + assign Q = (CE && !CLR) ? D : \$pastQ ; endmodule (* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE,D,Q,\\$pastQ" *) @@ -134,10 +128,7 @@ endmodule (* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1,D,Q,\\$pastQ" *) module \$__ABC_FDPE_1 (output Q, input C, CE, D, PRE, \$pastQ ); parameter [0:0] INIT = 1'b0; - //parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_PRE_INVERTED = 1'b0; - assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ; + assign Q = (CE && !PRE) ? D : \$pastQ ; endmodule `endif |