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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 12:32:33 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 12:32:33 -0700 |
| commit | 58bb84e5b22ba66310fd54fecdbf5817138a5fd1 (patch) | |
| tree | e12bff70410a62ea9d023e526db019651a367af6 /techlibs/xilinx | |
| parent | 521971e32ef54fa64474a8ed1c2748572901aaf5 (diff) | |
| download | yosys-58bb84e5b22ba66310fd54fecdbf5817138a5fd1.tar.gz yosys-58bb84e5b22ba66310fd54fecdbf5817138a5fd1.tar.bz2 yosys-58bb84e5b22ba66310fd54fecdbf5817138a5fd1.zip | |
Add some spacing
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 82399be08..2eb9fa2c1 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -220,15 +220,15 @@ module \$__XILINX_SHIFTX (A, B, Y); // This has the effect of more effectively utilising the hard mux; // take for example a 5:1 multiplexer, currently this would map as: // - // A[0] \___ __ A[0] \__ __ - // A[4] / \| \ whereas the more A[1] / \| \ - // A[1] _____| | obvious mapping A[2] \___| | - // A[2] _____| |-- of MSBs to hard A[3] / | |__ - // A[3]______| | resources would A[4] ____| | - // |__/ lead to: 1'bx ____| | - // || |__/ - // || || - // B[1:0] B[1:2] + // A[0] \___ __ A[0] \__ __ + // A[4] / \| \ whereas the more A[1] / \| \ + // A[1] _____| | obvious mapping A[2] \___| | + // A[2] _____| |-- of MSBs to hard A[3] / | |__ + // A[3]______| | resources would A[4] ____| | + // |__/ lead to: 1'bx ____| | + // || |__/ + // || || + // B[1:0] B[1:2] // // Expectation would be that the 'forward' mapping (right) is more // area efficient (consider a 9:1 multiplexer using 2x4:1 multiplexers |