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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-11 13:55:47 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-11 13:55:47 -0700 |
| commit | 854333f2af53626e09de693f5d5c7fa107d81c74 (patch) | |
| tree | 2989dc27dc1f2043f05207b01159b7724931bf2c /techlibs/xilinx | |
| parent | 8f9d529929f43e6ba98f06159ae9533984c6264f (diff) | |
| download | yosys-854333f2af53626e09de693f5d5c7fa107d81c74.tar.gz yosys-854333f2af53626e09de693f5d5c7fa107d81c74.tar.bz2 yosys-854333f2af53626e09de693f5d5c7fa107d81c74.zip | |
Propagate INIT attr
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/abc_ff.v | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v index 69013f475..19f86365a 100644 --- a/techlibs/xilinx/abc_ff.v +++ b/techlibs/xilinx/abc_ff.v @@ -27,7 +27,7 @@ module FDRE (output reg Q, input C, CE, D, R); parameter [0:0] IS_R_INVERTED = 1'b0; wire \$nextQ ; \$__ABC_FDRE #( - .INIT(|0), + .INIT(INIT), .IS_C_INVERTED(IS_C_INVERTED), .IS_D_INVERTED(IS_D_INVERTED), .IS_R_INVERTED(IS_R_INVERTED), @@ -57,7 +57,7 @@ module FDCE (output reg Q, input C, CE, D, CLR); parameter [0:0] IS_CLR_INVERTED = 1'b0; wire \$nextQ , \$currQ ; \$__ABC_FDCE #( - .INIT(|0), + .INIT(INIT), .IS_C_INVERTED(IS_C_INVERTED), .IS_D_INVERTED(IS_D_INVERTED), .IS_CLR_INVERTED(IS_CLR_INVERTED), @@ -73,7 +73,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; wire \$nextQ , \$currQ ; \$__ABC_FDCE_1 #( - .INIT(|0), + .INIT(INIT), .\$abc_flop_clk_pol (1'b1), .\$abc_flop_en_pol (1'b1) ) _TECHMAP_REPLACE_ ( @@ -90,7 +90,7 @@ module FDPE (output reg Q, input C, CE, D, PRE); parameter [0:0] IS_PRE_INVERTED = 1'b0; wire \$nextQ , \$currQ ; \$__ABC_FDPE #( - .INIT(|0), + .INIT(INIT), .IS_C_INVERTED(IS_C_INVERTED), .IS_D_INVERTED(IS_D_INVERTED), .IS_PRE_INVERTED(IS_PRE_INVERTED), @@ -106,7 +106,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; wire \$nextQ , \$currQ ; \$__ABC_FDPE_1 #( - .INIT(|0), + .INIT(INIT), .\$abc_flop_clk_pol (1'b1), .\$abc_flop_en_pol (1'b1) ) _TECHMAP_REPLACE_ ( |