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techlibs
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xilinx
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Author
Age
Files
Lines
*
Fix typo in check_label()
Eddie Hung
2019-10-04
1
-1
/
+1
*
Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`
Eddie Hung
2019-10-04
1
-2
/
+6
*
Remove DSP48E1 from *_cells_xtra.v
Eddie Hung
2019-10-04
3
-178
/
+2
*
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
Eddie Hung
2019-09-30
6
-122
/
+46
*
synth_xilinx: Support latches, remove used-up FF init values.
Marcin KoĆcielnicki
2019-09-30
2
-2
/
+76
*
Merge pull request #1359 from YosysHQ/xc7dsp
Eddie Hung
2019-09-29
11
-21
/
+3000
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*
Re-order
Eddie Hung
2019-09-27
1
-1
/
+1
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*
Typo
Eddie Hung
2019-09-26
1
-1
/
+1
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*
select once
Eddie Hung
2019-09-26
1
-3
/
+5
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*
Stop trying to be too smart by prematurely optimising
Eddie Hung
2019-09-26
1
-1
/
+3
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*
Call 'wreduce' after mul2dsp to avoid unextend()
Eddie Hung
2019-09-25
1
-0
/
+1
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*
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
Eddie Hung
2019-09-25
1
-1
/
+1
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*
Add (* techmap_autopurge *) to abc_unmap.v too
Eddie Hung
2019-09-23
1
-11
/
+11
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*
Add techmap_autopurge to outputs in abc_map.v too
Eddie Hung
2019-09-23
1
-11
/
+11
|
*
Revert "Add a xilinx_finalise pass"
Eddie Hung
2019-09-23
3
-87
/
+0
|
*
Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"
Eddie Hung
2019-09-23
1
-38
/
+38
|
*
Revert "Vivado does not like zero width port connections"
Eddie Hung
2019-09-23
1
-2
/
+2
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*
Vivado does not like zero width port connections
Eddie Hung
2019-09-23
1
-2
/
+2
|
*
Remove (* techmap_autopurge *) from abc_unmap.v since no effect
Eddie Hung
2019-09-23
1
-38
/
+38
|
*
Add a xilinx_finalise pass
Eddie Hung
2019-09-23
3
-0
/
+87
|
*
Grammar
Eddie Hung
2019-09-20
1
-1
/
+1
|
*
Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40
Eddie Hung
2019-09-20
1
-1
/
+1
|
*
Tidy up, fix undriven
Eddie Hung
2019-09-19
1
-32
/
+34
|
*
$__ABC_REG to have WIDTH parameter
Eddie Hung
2019-09-19
2
-17
/
+18
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*
Fix DSP48E1 timing by breaking P path if MREG or PREG
Eddie Hung
2019-09-19
4
-349
/
+363
|
*
Revert "Different approach to timing"
Eddie Hung
2019-09-19
4
-195
/
+405
|
*
Different approach to timing
Eddie Hung
2019-09-19
4
-405
/
+195
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*
Suppress $anyseq warnings
Eddie Hung
2019-09-19
1
-15
/
+32
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*
Use (* techmap_autopurge *) to suppress techmap warnings
Eddie Hung
2019-09-19
2
-94
/
+99
|
*
D is 25 bits not 24 bits wide
Eddie Hung
2019-09-19
1
-1
/
+1
|
*
Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
Eddie Hung
2019-09-19
8
-90
/
+502
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*
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synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2
Eddie Hung
2019-09-19
1
-1
/
+4
|
*
|
Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung
2019-09-18
7
-941
/
+19252
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*
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Fix copy-paste
Eddie Hung
2019-09-18
1
-2
/
+2
|
*
|
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Mis-spell
Eddie Hung
2019-09-18
1
-10
/
+25
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*
|
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Add pattern detection support for DSP48E1 model, check against vendor
Eddie Hung
2019-09-18
3
-8
/
+102
|
*
|
|
Add `undef DSP48E1_INST
Eddie Hung
2019-09-13
1
-4
/
+5
|
*
|
|
Fix D -> P{,COUT} delay
Eddie Hung
2019-09-13
1
-43
/
+43
|
*
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Add no MULT no DPORT config
Eddie Hung
2019-09-13
4
-226
/
+471
|
*
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Add support for MULT and DPORT
Eddie Hung
2019-09-13
4
-10
/
+588
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*
|
|
Refine diagram
Eddie Hung
2019-09-13
1
-12
/
+14
|
*
|
|
Add an ASCII drawing
Eddie Hung
2019-09-12
1
-3
/
+22
|
*
|
|
Finish explanation
Eddie Hung
2019-09-12
2
-5
/
+20
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*
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Rename to techmap_guard
Eddie Hung
2019-09-12
1
-2
/
+3
|
*
|
|
Initial DSP48E1 box support
Eddie Hung
2019-09-12
4
-0
/
+867
|
*
|
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Set more ports explicitly
Eddie Hung
2019-09-12
1
-1
/
+2
|
*
|
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Missing space
Eddie Hung
2019-09-11
1
-0
/
+1
|
*
|
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Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung
2019-09-11
5
-53
/
+219
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\
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*
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Move "(skip if -nodsp)" message to label
Eddie Hung
2019-09-10
1
-4
/
+4
|
*
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|
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Really get rid of 'opt_expr -fine' by being explicit
Eddie Hung
2019-09-10
1
-3
/
+0
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