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Author
Age
Files
Lines
*
Use C++11 final/override keywords.
whitequark
2020-06-18
2
-7
/
+7
*
xilinx: tidy up cells_sim.v a little
Eddie Hung
2020-05-25
1
-5
/
+7
*
Add force_downto and force_upto wire attributes.
Marcelina Kościelnicka
2020-05-19
4
-0
/
+33
*
xilinx: gate specify/attributes from iverilog
Eddie Hung
2020-05-14
1
-1
/
+3
*
xilinx/ice40/ecp5: zinit requires selected wires, so select them all
Eddie Hung
2020-05-14
1
-2
/
+2
*
xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells
Eddie Hung
2020-05-14
1
-1
/
+19
*
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
Eddie Hung
2020-05-14
6
-761
/
+127
*
synth_*: no need to explicitly read +/abc9_model.v
Eddie Hung
2020-05-14
1
-1
/
+1
*
abc9_ops: -prep_dff_map to error if async flop found
Eddie Hung
2020-05-14
1
-4
/
+0
*
Uncomment negative setup times; clamp to zero for connectivity
Eddie Hung
2020-05-14
1
-13
/
+29
*
synth_xilinx: rename dff_mode -> dff
Eddie Hung
2020-05-14
1
-8
/
+10
*
abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes
Eddie Hung
2020-05-14
4
-366
/
+5
*
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
Eddie Hung
2020-05-04
1
-3
/
+5
*
xilinx: improve xilinx_dffopt message
Eddie Hung
2020-04-22
1
-3
/
+6
*
Use default parameter value in getParam
Marcelina Kościelnicka
2020-04-21
1
-3
/
+3
*
Get rid of dffsr2dff.
Marcelina Kościelnicka
2020-04-15
1
-2
/
+1
*
Merge pull request #1648 from YosysHQ/eddie/cmp2lcu
Eddie Hung
2020-04-03
1
-2
/
+1
|
\
|
*
synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'
Eddie Hung
2020-04-03
1
-2
/
+1
*
|
kernel: big fat patch to use more ID::*, otherwise ID(*)
Eddie Hung
2020-04-02
1
-13
/
+13
|
/
*
xilinx: Mark IOBUFDS.IOB as external pad
Marcin Kościelnicki
2020-03-20
2
-1
/
+2
*
xilinx: consider DSP48E1.ADREG
Eddie Hung
2020-03-04
4
-5
/
+8
*
xilinx: cleanup DSP48E1 handling for abc9
Eddie Hung
2020-03-04
3
-86
/
+125
*
xilinx: improve specify for DSP48E1
Eddie Hung
2020-03-04
1
-32
/
+116
*
xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v
Eddie Hung
2020-03-04
2
-5
/
+14
*
Remove RAMB{18,36}E1 from cells_xtra.py
Eddie Hung
2020-02-27
1
-2
/
+2
*
xilinx: Update RAMB* specify entries
Eddie Hung
2020-02-27
1
-11
/
+42
*
xilinx: add delays to INV
Eddie Hung
2020-02-27
1
-0
/
+3
*
Make +/xilinx/cells_sim.v legal
Eddie Hung
2020-02-27
1
-76
/
+78
*
Get rid of (* abc9_{arrival,required} *) entirely
Eddie Hung
2020-02-27
3
-530
/
+496
*
abc9_ops: use TimingInfo for -prep_{lut,box} too
Eddie Hung
2020-02-27
1
-7
/
+10
*
Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy
Eddie Hung
2020-02-27
1
-14
/
+12
*
Fix tests by gating some specify constructs from iverilog
Eddie Hung
2020-02-27
1
-0
/
+16
*
abc9_ops: ignore (* abc9_flop *) if not '-dff'
Eddie Hung
2020-02-27
1
-2
/
+6
*
Update xilinx for ABC9
Eddie Hung
2020-02-27
3
-20
/
+16
*
Fix commented out specify statement
Eddie Hung
2020-02-27
1
-6
/
+6
*
xilinx: improve specify functionality
Eddie Hung
2020-02-27
5
-446
/
+519
*
xilinx: use specify blocks in place of abc9_{arrival,required}
Eddie Hung
2020-02-27
1
-176
/
+404
*
Auto-generate .box/.lut files from specify blocks
Eddie Hung
2020-02-27
7
-426
/
+151
*
abc9_ops: -prep_box, to be called once
Eddie Hung
2020-02-27
1
-1
/
+1
*
abc9_ops: -prep_lut and -write_lut to auto-generate LUT library
Eddie Hung
2020-02-27
2
-4
/
+85
*
xilinx: mark IOBUFDSE3 IOB pin as external
Piotr Binkowski
2020-02-27
2
-1
/
+2
*
abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr
Eddie Hung
2020-02-13
1
-11
/
+12
*
abc9: cleanup
Eddie Hung
2020-02-10
1
-40
/
+40
*
Remove unnecessary comma
Eddie Hung
2020-02-07
1
-3
/
+2
*
xilinx: Add support for LUT RAM on LUT4-based devices.
Marcin Kościelnicki
2020-02-07
4
-27
/
+22
*
xilinx: Initial support for LUT4 devices.
Marcin Kościelnicki
2020-02-07
3
-53
/
+152
*
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
Marcin Kościelnicki
2020-02-07
11
-1
/
+370
*
xilinx: Add support for Spartan 3A DSP block RAMs.
Marcin Kościelnicki
2020-02-07
3
-1
/
+39
*
Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk
Eddie Hung
2020-02-06
1
-4
/
+5
*
Fix/cleanup +/xilinx/arith_map.v
Eddie Hung
2020-02-06
1
-111
/
+44
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