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* xilinx: Fix srl regression.Marcelina Kościelnicka2020-07-121-2/+2
* xilinx: Use dfflegalize.Marcelina Kościelnicka2020-07-096-484/+131
* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-234-50/+50
* Use C++11 final/override keywords.whitequark2020-06-182-7/+7
* xilinx: tidy up cells_sim.v a littleEddie Hung2020-05-251-5/+7
* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-194-0/+33
* xilinx: gate specify/attributes from iverilogEddie Hung2020-05-141-1/+3
* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-141-2/+2
* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-141-1/+19
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-146-761/+127
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+1
* abc9_ops: -prep_dff_map to error if async flop foundEddie Hung2020-05-141-4/+0
* Uncomment negative setup times; clamp to zero for connectivityEddie Hung2020-05-141-13/+29
* synth_xilinx: rename dff_mode -> dffEddie Hung2020-05-141-8/+10
* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-144-366/+5
* synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-041-3/+5
* xilinx: improve xilinx_dffopt messageEddie Hung2020-04-221-3/+6
* Use default parameter value in getParamMarcelina Kościelnicka2020-04-211-3/+3
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-2/+1
* Merge pull request #1648 from YosysHQ/eddie/cmp2lcuEddie Hung2020-04-031-2/+1
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| * synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'Eddie Hung2020-04-031-2/+1
* | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-13/+13
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* xilinx: Mark IOBUFDS.IOB as external padMarcin Kościelnicki2020-03-202-1/+2
* xilinx: consider DSP48E1.ADREGEddie Hung2020-03-044-5/+8
* xilinx: cleanup DSP48E1 handling for abc9Eddie Hung2020-03-043-86/+125
* xilinx: improve specify for DSP48E1Eddie Hung2020-03-041-32/+116
* xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.vEddie Hung2020-03-042-5/+14
* Remove RAMB{18,36}E1 from cells_xtra.pyEddie Hung2020-02-271-2/+2
* xilinx: Update RAMB* specify entriesEddie Hung2020-02-271-11/+42
* xilinx: add delays to INVEddie Hung2020-02-271-0/+3
* Make +/xilinx/cells_sim.v legalEddie Hung2020-02-271-76/+78
* Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-273-530/+496
* abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-7/+10
* Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happyEddie Hung2020-02-271-14/+12
* Fix tests by gating some specify constructs from iverilogEddie Hung2020-02-271-0/+16
* abc9_ops: ignore (* abc9_flop *) if not '-dff'Eddie Hung2020-02-271-2/+6
* Update xilinx for ABC9Eddie Hung2020-02-273-20/+16
* Fix commented out specify statementEddie Hung2020-02-271-6/+6
* xilinx: improve specify functionalityEddie Hung2020-02-275-446/+519
* xilinx: use specify blocks in place of abc9_{arrival,required}Eddie Hung2020-02-271-176/+404
* Auto-generate .box/.lut files from specify blocksEddie Hung2020-02-277-426/+151
* abc9_ops: -prep_box, to be called onceEddie Hung2020-02-271-1/+1
* abc9_ops: -prep_lut and -write_lut to auto-generate LUT libraryEddie Hung2020-02-272-4/+85
* xilinx: mark IOBUFDSE3 IOB pin as externalPiotr Binkowski2020-02-272-1/+2
* abc9: deprecate abc9_ff.init wire for (* abc9_init *) attrEddie Hung2020-02-131-11/+12
* abc9: cleanupEddie Hung2020-02-101-40/+40
* Remove unnecessary commaEddie Hung2020-02-071-3/+2
* xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-074-27/+22
* xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-073-53/+152
* xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.Marcin Kościelnicki2020-02-0711-1/+370