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* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-141-2/+2
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-3/+1
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+1
* synth_xilinx: rename dff_mode -> dffEddie Hung2020-05-141-8/+10
* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-141-4/+1
* synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-041-3/+5
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-2/+1
* synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'Eddie Hung2020-04-031-2/+1
* Update xilinx for ABC9Eddie Hung2020-02-271-1/+1
* xilinx: improve specify functionalityEddie Hung2020-02-271-2/+2
* Auto-generate .box/.lut files from specify blocksEddie Hung2020-02-271-1/+1
* abc9_ops: -prep_box, to be called onceEddie Hung2020-02-271-1/+1
* abc9_ops: -prep_lut and -write_lut to auto-generate LUT libraryEddie Hung2020-02-271-4/+2
* Remove unnecessary commaEddie Hung2020-02-071-3/+2
* xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-071-2/+1
* xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-071-16/+82
* xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.Marcin Kościelnicki2020-02-071-1/+8
* xilinx: Add support for Spartan 3A DSP block RAMs.Marcin Kościelnicki2020-02-071-1/+6
* Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-031-0/+1
* synth_xilinx: cleanup helpEddie Hung2020-01-281-6/+4
* synth_xilinx: fix help when no active_design; fixes #1664Eddie Hung2020-01-281-2/+3
* Fix unresolved conflict from #1573Eddie Hung2020-01-281-1/+1
* Merge pull request #1573 from YosysHQ/eddie/xilinx_tristateN. Engelhardt2020-01-281-0/+3
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| * Duplicate tribuf call, credit to @mwkmwkmwkEddie Hung2019-12-131-1/+0
| * synth_xilinx: error out if tristate without '-iopad'Eddie Hung2019-12-121-0/+4
* | Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623Eddie Hung2020-01-171-2/+0
* | Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_WMiodrag Milanović2020-01-151-1/+1
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| * | synth_xilinx: fix default W value for non-xc7Eddie Hung2020-01-141-1/+1
* | | Merge pull request #1623 from YosysHQ/mmicko/edif_attrMiodrag Milanović2020-01-141-1/+1
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| * | Use CARRY4 for abc1 as well, preventing issues with VivadoMiodrag Milanovic2020-01-101-1/+1
* | | Another conflictEddie Hung2020-01-111-1/+0
* | | synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macroEddie Hung2020-01-101-4/+11
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* | synth_xilinx -dff to work with abc tooEddie Hung2020-01-021-6/+14
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-021-3/+3
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| * \ Merge pull request #1601 from YosysHQ/eddie/synth_retimeEddie Hung2020-01-021-3/+3
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| | * | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
| | * | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-2/+2
* | | | abc9 -keepff -> -dff; refactor dff operationsEddie Hung2020-01-021-3/+3
* | | | Restore abc9 -keepffEddie Hung2020-01-011-1/+3
* | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-301-12/+10
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| * | | Merge remote-tracking branch 'origin/master' into iopad_defaultMiodrag Milanovic2019-12-281-1/+4
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| | * | xilinx_dsp: Initial DSP48A/DSP48A1 support.Marcin Kościelnicki2019-12-221-1/+4
| * | | Addressed review commentsMiodrag Milanovic2019-12-211-2/+3
| * | | iopad no op for compatibility with old scriptsMiodrag Milanovic2019-12-211-0/+3
| * | | Make iopad option default for all xilinx flowsMiodrag Milanovic2019-12-211-14/+5
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| * | Revert "Optimise write_xaiger"Eddie Hung2019-12-201-5/+0
| * | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-191-0/+5
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| | * | techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-061-0/+5
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* | | Add "synth_xilinx -dff" option, cleanup abc9Eddie Hung2019-12-301-2/+14
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-191-4/+12
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