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| author | Marcin Kościelnicki <mwk@0x04.net> | 2020-02-03 18:37:28 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-02-07 09:03:22 +0100 |
| commit | 89adef352fde57fa599d66fe404c3c2b9e607a7f (patch) | |
| tree | 57dc27856458c388187570d43178f43f3503bb46 /techlibs/xilinx/synth_xilinx.cc | |
| parent | d48950d92d748cc24ecfefc5beab19ea899982df (diff) | |
| download | yosys-89adef352fde57fa599d66fe404c3c2b9e607a7f.tar.gz yosys-89adef352fde57fa599d66fe404c3c2b9e607a7f.tar.bz2 yosys-89adef352fde57fa599d66fe404c3c2b9e607a7f.zip | |
xilinx: Add support for LUT RAM on LUT4-based devices.
There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.
Fixes #1549
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index fe58eb6d3..556f85a20 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -318,7 +318,6 @@ struct SynthXilinxPass : public ScriptPass if (lut_size != 6) { log_warning("Shift register inference not yet supported for family %s.\n", family.c_str()); nosrl = true; - nolutram = true; } if (widemux != 0 && widemux < 2) @@ -518,7 +517,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_lutram", "(skip if '-nolutram')")) { if (!nolutram || help_mode) { - run("memory_bram -rules +/xilinx/lutrams.txt"); + run("memory_bram -rules +/xilinx/lut" + lut_size_s + "_lutrams.txt"); run("techmap -map +/xilinx/lutrams_map.v"); } } |