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| author | Marcin Kościelnicki <mwk@0x04.net> | 2020-02-04 15:35:47 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-02-07 01:00:29 +0100 |
| commit | 30854b9c7f23e2817a445761022668d6b0f7c0ef (patch) | |
| tree | 83471ee10f31862015bab189c3684ade82e23c47 /techlibs/xilinx/synth_xilinx.cc | |
| parent | 95c46ccc555769cd9d24bae27e0b7264f06e3d66 (diff) | |
| download | yosys-30854b9c7f23e2817a445761022668d6b0f7c0ef.tar.gz yosys-30854b9c7f23e2817a445761022668d6b0f7c0ef.tar.bz2 yosys-30854b9c7f23e2817a445761022668d6b0f7c0ef.zip | |
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 705591cf7..a7fa73837 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -438,7 +438,14 @@ struct SynthXilinxPass : public ScriptPass run("memory_bram -rules +/xilinx/{family}_brams.txt"); run("techmap -map +/xilinx/{family}_brams_map.v"); } else if (!nobram) { - if (family == "xc3sda") { + if (family == "xc2v" || family == "xc2vp" || family == "xc3s" || family == "xc3se") { + run("memory_bram -rules +/xilinx/xc2v_brams.txt"); + run("techmap -map +/xilinx/xc2v_brams_map.v"); + } else if (family == "xc3sa") { + // Superset of Virtex 2 primitives — uses common map file. + run("memory_bram -rules +/xilinx/xc3sa_brams.txt"); + run("techmap -map +/xilinx/xc2v_brams_map.v"); + } else if (family == "xc3sda") { // Supported block RAMs for Spartan 3A DSP are // a subset of Spartan 6's ones. run("memory_bram -rules +/xilinx/xc3sda_brams.txt"); |