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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-11 11:38:49 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | 0e7c55e2a73f47d7f179d434ba79dd9e2bf9045b (patch) | |
| tree | 153bf13f2752a2501e49bef6d3166a83bc26aa22 /techlibs/xilinx/synth_xilinx.cc | |
| parent | 3d6603792dbd36ccb572403815b78121a7ad80e8 (diff) | |
| download | yosys-0e7c55e2a73f47d7f179d434ba79dd9e2bf9045b.tar.gz yosys-0e7c55e2a73f47d7f179d434ba79dd9e2bf9045b.tar.bz2 yosys-0e7c55e2a73f47d7f179d434ba79dd9e2bf9045b.zip | |
Auto-generate .box/.lut files from specify blocks
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index db39330ae..4011e09b0 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -619,7 +619,7 @@ struct SynthXilinxPass : public ScriptPass if (dff_mode) techmap_args += " -D DFF_MODE"; run("techmap " + techmap_args); - run("read_verilog -icells -lib +/xilinx/abc9_model.v"); + run("read_verilog -icells -specify -lib +/xilinx/abc9_model.v"); std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str()); if (active_design->scratchpad.count(k)) |